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Supero Super X8DTL-3 User Manual

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Chapter 1: Introduction
1-3
Notes
The DOM Power connector (JWF1) and the Wake-On-Ring header (JWOR), 1.
are supported by the PCB Rev. 2.01 or a newer version board only.
SAS Ports, SAS jumpers, the I-Button, and the LSI 1068E chip are available 2.
on the X8DTL-3/-3F only. For SAS RAID con guration, refer to the LSI User
Guide posted at our website at http://www.supermicro.com/support/manuals/
IPMI 2.0, the PHY chip, and the Dedicated LAN (w/KVM support) are avail-3.
able on the X8DTL-3F/-iF only. For mo+re information, refer to the IPMI user
guide posted on our website at http://www.supermicro.com/support/manuals/.
X8DTL-3/X8DTL-i/X8DTL-3F/X8DTL-iF Layout
JPW3
JPW2
JBT1
JPI2C
COM1
I-SATA0
I-Button
JPS1
JWD
JPL2
JPL1
JF1
SP1
1
JWOL
LE1
D20
JBAT1
JP3
JL1
JPS2
JOH1
JPB
JP5
J16
JD1
CPU1 FAN
Slot3 PCI-E 1.0 x4
7HG
5ADG
7TN100C
W8379
W8352
Slot6 PCI-E 2.0 x8 (in x16 Slot)
JI2C2
SAS6
SAS5
SAS4
SAS3
SAS2
SAS1
Slot4 PCI-E 2.0 x8
BMC CTRL
WPCM450-R
LC4128ZE-
ICH10R
(South Bridge)
5500
(North Bridge)
LES2
P1-DIMM3A
P1-DIMM1A
P2-DIMM3A
P1-DIMM2A
P2-DIMM2A
P2-DIMM1A
KB/Mouse
USB0/1
VGA
LAN1
UID
LE2
Slot2 PCI 33MHz
Slot1 PCI 33MHz
COM2
IPMB
USB4/5
USB6
T-SGPIO2
USB2/3
I-SATA5
T-SGPIO1
I-SATA3
I-SATA2
I-SATA4
I-SATA1
3-SGPIO2
3-SGPIO1
LSI SAS1068E
SAS0
FAN5
FAN4
FAN6
FAN1/
CPU2
LAN2
IPMI LAN
LAN
CTRL
SAS7
JI2C1
LAN
CTRL
PHY
Chip
CPU1
Intel
Intel
JPW1
CPU2FAN
FAN2/
BIOS
Slot5 PCI-E 2.0 x4 (in x8 Slot)
X8DTL Series
Flash ROM
BMC
Battery
Buzzer
1
FAN3
JPG1
(in x8 Slot)
Rev. 2.01
JWOR
JWF1

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Supero Super X8DTL-3 Specifications

General IconGeneral
BrandSupero
ModelSuper X8DTL-3
CategoryMotherboard
LanguageEnglish

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