Chapter 1: Introduction
1-9
1-2 Chipset Overview
Built upon the functionality and the capability of the 5500 platform, the X8DTL-3/
X8DTL-i/X8DTL-3F/X8DTL-iF motherboard provides the performance and fea-
ture set required for dual-processor-based high-end systems with confi guration
optimized for HCP/Cluster systems and intensive applications. The 5500 platform
consists of the 5500/5600 Series (LGA 1366) processor, the IOH-24D (I/O Hub),
and the ICH10R (South Bridge). With the Intel QuickPath Interconnect (QPI) con-
troller built in, the 5500 platform is the fi rst dual-processing platform that offers
the next generation point-to-point system interconnect interface, replacing the
current Front Side Bus Technology, substantially enhancing system performance
with increased bandwidth and scalability.
The IOH-24D connects to each processor through an independent QuickPath
Interconnect (QPI) link. Each link consists of 20 pairs of unidirectional differential
lanes for transmission and receiving in addition to a differential forwarded clock.
A full-width QPI link pair provides 84 signals. Each processor supports two Quick-
Path links, one going to the other processor and the other to the IOH-24D chip.
The 5500 Platform supports PCI Express Gen2 lanes, peer-to-peer read and write
transactions. The ICH10R provides up to 6 PCI-Express ports, six SATA ports
and 10 USB connections.
In addition, the 5500 platform also offers a wide range of RAS (Reliability, Avail-
ability and Serviceability) features. These features include memory interface ECC,
x4/x8 Single Device Data Correction (SDDC), Cyclic Redundancy Check (CRC),
parity protection, out-of-band register access via SMBus, memory mirroring, and
Hot-plug support on the PCI-Express Interface.
Main Features of the 5500/5600* Series Processor and the
5500 Chipset
Four processor cores in each processor with 8MB shared cache among cores•
Two full-width Intel QuickPath interconnect links, up to 6.4 GT/s of data transfer •
rate in each direction
Virtualization Technology, Integrated Management Engine supported
•
Point-to-point cache coherent interconnect, Fast/narrow unidirectional links, and •
Concurrent bi-directional traffi c
Error detection via CRC and Error correction via Link level retry
•
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