Supero X10DRL-i - Chipset Configuration; North Bridge; Iio Configuration

Chapter 4: AMI BIOS
4-11
than P0, with its frequency and voltage scaled back a notch. The options are
Between P1/P0 and Below P1.
Chipset Conguration
Warning! Please set the correct settings for the items below. A wrong conguration
setting may cause the system to become malfunction.
North Bridge
This feature allows the user to congure the settings for the Intel North Bridge.
IIO Conguration
EV DFX (Device Function On-Hide) Feature
When this feature is set to Enable, the EV_DFX Lock Bits that are located on a
processor will always remain clear during electric tuning. The options are Dis-
able and Enable.
IIO1 Conguration
CPU1 SLOT2 PCI-E 3.0 X8
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU1 SLOT3 PCI-E 3.0 X8
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU1 SLOT6 PCI-E 3.0 X8
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU1 SLOT5 PCI-E 3.0 X16
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
IIO2 Conguration
CPU2 SLOT4 PCI-E 3.0 X4 (IN X8)
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).