Technics SL-P110 - Page 20

e MN6617 (Digital Signal Processing : EFM Decoder, Error Correction, CLV Servo)
Pin 1/0 . Pin 1/0 .
No. Mark Devision Function No. Mark Devision Function
Sub-code block {Q data) clock 16-bit data output/Synchronizing
1 BLKCK 0 (75 Hz) 34 DAB/FCLV 0 detection signal (Not used)
— Sub-code frame {Q data} clock DA7/ 16-bit data output/interpolation
2 | CLDCK o (7.35 kHz) 35 | pBYTE O | flag for each byte (Not used)
3 suBQ [s] Sub-code (Q data) output 16-bit data output/
36 | DAB/IPSEL MO | interpolation inhibit (Not used)
4 CRC o (Sub-code (Q dat;x) CRC check
Not used, open 16-bit data output/C2 decoder
37 DAS/FLAGS 0 correction flag 3 (Not used)
5 RST | Reset signal input {reset at “'L"’)
16-bit data output/C2 decoder
6 MLD [ Command load input 38 DA4/FLAG4 0 correction flag 2 (Not used)
7 MCLK | Command clock input 16-bit data output/C2 decoder
39 DA3/FLAG3 0 correction flag 1 (Not used)
8 MDATA 1 Command data input
16-bit data output/C1 decoder
9 DMUTE { Muting control {muting ON at “'H"’) 40 DA2/FLAG2 o correction flag 2 (Not used)
vy Tracking servo ON signal 16-bit data output/C1 decoder
10 TRON ! {tracking servo ON at 'L’} ! DA1/FLAG1 0 correction flag 1 (Not used)
Processing condition (CRC, OTC, 16-bit data output/Crystal frame
1| STAT © | cLVOK, TT STOP) output 42 | DAO/FLCKO O | clock
12 SMCK [0} Clock output (4.2336 MHz) 43 D7
p—— = ctock § [§ 1/0 16 K RAM data output
itch control cl output 50 DO
13 PMCK (o] {Not used, open) __
51 RAMOE 16 K RAM OE signal
14 ITC ! Track counter input signal —
(Not used, connected to +5V) 52 | RAMWE 16 K RAM WE signa!
——a Test mode selection 53 RAMA 0 :
15 TEST | (Not used, connected to +5V) ¢ § 16 K RAM address signal
’ 0 . .
63 RAMA10 (RAMAO : LSB, RAMA10: MSB)
16 X2 (o} Clock output (16.9334 MHz)
64 PC o Spindle motor ON signal
17 X1 | Clock input (16.9344 MHz) {(ON at ""'L")
18
|
sEL
i
DA
output
parallel/serial
selection
6
|
EC
0
Spindle
motor
drive
signal
{serial at 'L"’)
Len ' deal Y 66 FG | Spindle motor FG signal input
channel deglitch signal/serial
19 LDG/WDCK o data word clock. 67 —_— B
20 RDG (o] R channel deglitch signal. 68 _ —_—
De-emphasis ON signal 69 _— —_—
7 DEMPH o (de-emphasis ON at ""H"’)
70 —_— —_—
Interpolation flag
22 IPFLAG 0 (interpolation at ““H"’) 71 _— —_—
23 FLAGO 0 Error flag (error at "H") 72 PCK 1 PLL extract clock input
16 K RAM address reset signal
24 FLAGE 0 (reset at “"H’’} 73 vDD 1 Power supply (connected to +5V)
Ciock {16.9334 MHz) output 74 EFM | EFM signal input (PLL)
£ XCK 0o {Not used, open)
75 SRF t EFM signal input {DSL)
2% DA15/ o 16-bit data output/serial data
SRDATA output (MSB first) 76 DO t Drop-out signal {Drop-out at “H**)
37 DA14/ o 16-bit data output/serial data 77 CLVS 11T stereo OK signal (OK at "‘H"’}
SRDATAX output {LSB first)
6o d p 4 78 FPC (0] PLL frequency comparision signal
it data output/serial data
» DA13/SRCK ° beat clock. 79 BSSEL o ZlgnLalfrequency in take operation
16-bit data output/serial data .
29 | DA12/WDCK 0 word clock {Not used) 80 —_ —_—
30 DA11/ o 16-bit data output/serial data 81 _— —_—
BYTCK byte clock (Not used)}
82 —_— e
31 GND | GND terminal
32 | DA1O/RIL o 16-bit data output/RIL signal 83 | susC 0 Sub-code serial output data
33 DA9/RESY 0 16-bit data output/ 84 SBCK | Clock for sub-code serial output
Resynchronizing signal