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PART
II
CONTENTS
1.
PLL
Synthesizer
.
Synthesizer
Block
diagram of synthesizer section.
i
-3
Interface
circuit.
Prescaler
Programmable
frequency
divider. . ,
1-5-1
Operational description
of
lG
1-5-2
Frequency division in fixed code
pressetting.
.
.
. . .
1-5-3 Frequency division
in variable
code
presetting
.
.
. .
1-5-4
Programmable frequency dividing ratio.
.
. .
1-5-5
Faulty operation
prevent¡ng
eircuit.
1-6 Crystal
frequency divider .
1-7
Phase comparator
and low-pass filter.
1-1
1-2
1
1
1
1
2
3
3
5
7
I
I
I
11
1-4
1-5
2-2
3-4
3-5
1-7-1
1-7-2
Functions of
phase
detector, charge
pump
and
LPF
Shock
noise
preventing
circuit. .
. . .
.....10
.....10
.....11
1-8 VCO
(Voltage
control oscillator). . .
2. Circuit for start and stop
pulse
generation
in auto tuning, and adjacent
circuits
....12
2-1
station
selector step scan
2-1-1
Flip-flopcircuit.
.12
2-1-2 Start
pulse generation
(differential
circuit)
2-1-3 Stop
pulse generation
2-1-4 Adjacentcircuits
Operat¡ons
with station selector at
fine
and standard . . .
2-2-1 Outline
of auto tuning. . .
2-2-2 Clock
pulse
oscillator c¡rcuit and
adjacent
circuits
12
't3
14
14
16
17
.15
.16
2-2-3
Extraction
of
tuning
signal
3.
Operation
of the
tuning counter . . . . .
18
3-1 Operational
description of lC . . . .
3-2
3-3
and clock
pulse generator
3-3-1 Autotun¡ng.....
3-3-2
Step
scan. . .
3-3-3
Manual tuning
Counter
circuit
for frequency
code
3-4-1 Counteroperation.
3-4-2 Presettingoperation
3-4-3 Presetting operation
(for
the
United
States)
Last one
memory
4.
Frequency indicator circuit.
4-1
7-segment indicator tubes
32
32
33
4-2
Frequency
indication
I
4-3
Frequency
indication II. .
5" Bus line
....35
Tuning
frequency
section
M
code
S code
+B
code
6. Tuning
RS
latch
initial setting
circuit
5-1
5-2
5-3
5-4
18
23
24
25
25
26
27
28
29
30
31
32
35
36
36
36
37
397.
Schematic
Diagram
.sT.9038
(M),
(MC)
.sr-9038
(E),
(XE),
(XGF), (XGH), (XA),
(X)
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