Theory of Operation—2213 Service
emitter transistors Q331 and Q341 are converted to
voltages at the bases of Q335 and Q345 respectively.
Emitter-follower output transistors Q335 and Q345 then
drive the Delay Line through reverse terminations R335-
C335 and R345-C345. Amplifier compensation is provided
by R340 and C340, and shunt feedback is supplied by
R336 and R345.
Delay Line
Delay Line DL350 provides about 100 ns of delay in
the vertical signal. When using internal triggering (CH 1,
CH 2, or VERT MODE), the delay time allows the Sweep
Generator sufficient time to produce a sweep before the
vertical signal reaches the crt deflection plates. This feature
permits viewing the leading edge of the internal signal
that originates the trigger pulse.
Vertical Output Amplifier
The Vertical Output Amplifier, also shown on Diagram 3,
provides final amplification of the input signals for appli
cation to the deflection plates of the crt. Signals from the
Delay Line are applied to a differential amplifier input
stage composed of Q350 and Q360. The Delay Line is
terminated in the proper impedance by resistors R338 and
R348. Resistor R355 sets the gain of Q350 and Q360.
Thermal compensation of the stage gain is provided by
thermistor RT356, connected in series with R356 across
R355. The RC networks connected across R355 provide
both low- and high-frequency compensation of the stage.
The differential output is applied to output transistor
pairs Q376-Q377 and Q386-Q387. These transistors form a
common-emitter shunt-feedback amplifier stage, with
R376, R377, R386, and R387 serving as feedback elements.
Capacitors C377 and C387, connected across R377 and
R387 respectively, provide increasing negative feedback
as the signal frequency rises to lim it the amplifier band
width at the upper frequency limit. Output voltage from
the amplifier is divided between the two transistors of each
half. The signal voltage applied to the crt vertical deflection
plates is the sum of voltage drops across the pairs (Q376-
Q377 and Q386-Q387). The deflection voltage is pro
portional to the signal current driving the bases of Q376
and Q386.
BEAM FIND switch S390 (Diagram 6) normally supplies
—8.6 V directly to R390 to set the stage bias. When the
BEAM FIND button is pressed in and held, the direct
voltage is removed and the —8.6-V bias is provided via
series resistor R391. The output voltage swing is thereby
reduced to hold the vertical trace deflection to within the
graticule area.
Channel Switching Logic Circuit
The Channel Switching Logic circuitry composed of
U310A and U317A selects either Channel 1 or Channel 2
and various display modes for crt display via front-panel
switches and the X-Y position of the SEC/DIV switch.
When the instrument is not in the X-Y Mode, signal
line XY is grounded through contacts on the SEC/DIV
switch (Diagram 8). This action establishes LO logic levels
on pins C, B, and G of front-panel switch S317 (CH 1-
BOTH-CH 2) and on pins C and B of S305 (INT).
Switch S317 selects the vertical channel signal that
drives the Delay Line Driver via the Channel Diode Gates.
With S317 set to CH 1, a LO is applied to the Set input
(pin 4) of U317A. Flip-flop U317A will then be set, and
the Q output (pin 5) will be HI. Pin 5 of U317A is the CH 1
Enable signal line, and when it is HI, the Channel 1 vertical
signal is gated to the Delay Line Driver. When S317 is set
to CH 2, the Reset input o f U317A (pin 1) will be held LO
through CR705. The CH 2 Enable signal (U317A, pin 5) is
then set HI and the Channel 2 vertical signal is gated to the
Delay Line Driver.
Setting S317 to the BOTH position removes the LO
from both the Set and Reset inputs of U317A. This action
allows the channel selected for display to be determined
either by the logic level applied to the D input (pin 2) and
the clock applied to pin 3 or by the logic level applied to
the Set and Reset inputs from the ADD-ALT-CHOP switch.
The ADD-ALT-CHOP switch (S315) is enabled by the
LO placed on pins A, C, and F when the CH 1-BOTH-CH 2
switch is set to BOTH. When in ADD, S315 holds both the
Set and Reset input of U317A LO through CR706 and
CR701 respectively. The Q and Q outputs of U317A will
then be HI, and both Channel 1 and Channel 2 vertical
signals are gated to the Delay Line Driver. The signal
current is summed at the input to the Delay Line Driver,
and the resulting oscilloscope Add vertical display is the
algebraic sum of the two vertical signals.
The Add Enable circuit, composed of Q316, U197C,
and U315A, is activated when both Diode Gates are turned
on for an Add vertical display. With the Q and Q outputs
of U317A HI, the output of U315A will be LO and tran
sistor Q316 is biased on. The collector of Q316 rises toward
+5 V and U197C is biased on. Transistor U197C supplies
the additional current required to keep both Diode Gates
forward biased and to supply the proper dc level to the
Delay Line Driver input. Bypass capacitor C316 prevents
switching transients from being introduced into the Delay
Line Driver by the Add Enable circuit.
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