Tektronix 2213 - Page 32

C H
1
O
R Υ
s101
[AC -G N O-DC
HIGH - Ζ ATTENU
Λ
TO
R
S105
Q125,
Q133
ρ131, Q139
- Β . Β V ς D I V \ Γ - +8 . β V ς
R 138
STEP ΒΛ L
5
R 143
L OW -Ζ ATTENU Λ TO R

XI/X10 ΛΜΡ L
-8 .6 V ς
J V V4-
+8 . Β V ς
R146
X10 GAIN
382 β -21
F ig u re 3-2 . Detaile d bloc k d iagra m of the C ha nn el 1 atte nu ator a nd atte nu ato r switc h i n g ta b les .
C104 i n t h e 10 Χ attenuator and by C110 in t h e 100 Χ
attenuator . Switc h S105 B connects t h e a p p rop r iate
attenuator out put to t
h
e i
np
ut of t
h
e Bu
ffe r
Am
p lifier
.
B
uffer Am p lifier and Low- Ζ Attenuator
T
h e
B
uffer Amplifier presents α h ig h -imp e dance, low-
capacitance
load to t h e in p ut signal a nd d elivers an accurate
re p lica of t h at signal to α low-impedance buffer o u t p ut
circuit . T h e L ow- Ζ out put circ u it is composed of α 250- Ω
voltage-divider networ k ( R 139
F
t
h roug h R
139
J ) and t h e
V olts/Div V ar
circuit ( R 141, C141, and R 143) . Switc h
S105 B selects
t h e
ap p
ro p riate out p ut from t h e voltage
d ivider
.
T h
e
B
uffer Amplifier contains two p at h s : α slow
p at h consisting of
R
116, R
117, U 120, an dR 119 in parallel
wit
h
C119 ; an
d
α
fast pat h t h roug h C121 . T h e signals
t h roug h bot h p at h s are ap p lie d to t h e gate of Q122 .
T h eory of O p eration-2213 Service
In t h e slo
w - p
at
h p
ortio
n , t h e i np
ut
signal
is d ivi de d by
te n by t h e combination of R 117 and R 116 an d is t h en
a pp lie d to U 120 p in 3 . T
h
e B uffer Am p lifier out p u t signal
is also d ivi ded by ten by t h e combination of R 139 B ,
R 139C, R 139D, and R 139 N . S u fficient d c-gate bias for
input FE T Q122 is ge n erate d b y t h e slow- p at h circ u it to
produce α null (zero d ifference) between p ins 2 an d 3 of
U 120 . T h e closed-loop gain of t h e slow p at h is matc h ed to
t h e fast- p at h gain . If t h e average output voltage from t h e
fast p at h c h anges, transcon d uctance am p lifier U 120 a d j usts
t h e do gate b ias on Q122 to kee pU 120 p in 2 and U 120
pin 3 nulle d . T h is action keeps t h e slow-p at h and t h e
fast- p at h gains matc h e d . R esistor R 119 isolates t h e output
im p e d ance of U 120 from t h e in p ut of FE T 0122 . T h is iso-
latio n , i n com b inatio n wit h t h e h ig h in p u t im p e d ance of
U 120, p revents h ig h -fre q ue n cy loading of t h e in p ut signal .
Capacitor C119 com p ensates for t h e output ca p acitance
of U 120 .
3-
5
VO L TS/
D I V
Χ
1 Χ 10
2 mV Χ
5 m V Χ
10
mV Χ
20 mV Χ
50 mV Χ
100 mV
Χ
200
mV Χ
500 mV Χ
1 V Χ
2 V Χ
5 V Χ
10 V Χ
V O L
TS/
D I V
_
1 -
2 , 5
_
5
2 m V Χ
5 mV Χ
10
mV Χ
20 m V Χ
50 mV Χ
100 m V Χ
200
m V Χ
500 m V Χ
1 V Χ
2 V Χ
5 V Χ
Ι 10
V Ι Ι Ι Χ Ι
V
O L
TS/
_ 1 -
10 =1 00
D I V
2 m V Χ
5 mV Χ
10 mV Χ
20
m V Χ
50 m V Χ
100 mV Χ
200 mV Χ
500
mV Χ
1 V Χ
2V Χ
5V Χ
10 V
Χ
νοιτs/Dτν
__ __ Ι __-
Ι
___-
R141
CA L
Ι -
Ι
Ι
Ι
C H 1 I NPU
T
VOLTS/
C H 1+
Χ 1 /Χ 10
C H 1
VER T
BUFFER
L
OW- Ζ
DI V
ΛΜΡ L
SI G
AMPLIFIER ΛΤΤΕΝ U ΛΤΟ R
VA R
U 145
C H 1-
TO
U 12θ , Q122 -1 > -2 .5,
Ρ R ΕΛΜΡ