Tektronix 2213 - Page 39

T h eory of
Operation-2213 Se r vice
such , must also be
used to obtain t he internal vertical mode
trigger signal .
Wh en S305 is set to VER T
M
OD
E , t h e L
O
logic level on
t h e ΧΥ signal line is
remove d from both U305B p in 4 an d
from
U 305D pins 12 and 13, p ulling t hese i n puts ΗΙ . In
eit h er ADD or A LT VER TICA L M OD E, U 305C
pin
9 an
d
U305 B pi
n 5 are also p ulled ΗΙ w henever α L O is not
bei ng
applied
from 5315 .
T h e in pu t conditions j
ust desc r i b ed for U 305B , U 305D,
and U 305C allow t h
e logic levels
on
U315C p in 10 an d
U315 B pi
n 4
to
control t h e states of the CH 1 Trig an d
C H 2 Trig trigge
r -selection sig n als . In put sig n als to p i n s 10
and 4 are o b taine d
from
t
h e
C
hannel En able signals p rese n t
at pins 5 a nd 6 of C h
annel
Switc
h
U 317A .
Wh en CH 1
E
na b
le
is
ΗΙ (selecting t he C han nel 1 sig n al
for d isplay), U 315C p
in
10
is also ΗΙ a nd U 315C pi n 8 is
L O to d isable
t he
C
hannel 2 Trigger P ic k off Amplifier .
Concurrently U 317A p in 6
a
pp
lies α L O to U315B p in 4,
and the ΗΙ out p ut o btained
from U315Bp in 6 as α res u lt
enables the C hannel 1 Trigger
P
ic
k off Am p lifier .
F or A L T VER TICA L M OD
E
dis p
lays, t he out pu t states
of C hannel Switc h S317A
are switch e d alternatel y, at t h e
en d of each swee
p , in
sync
hronization with t h e Alt Sync
signal . T h erefore, on
alternate sweeps, t h e logic levels on
U 315C p in 10 and on U
315
B p
in 4 also c hange states .
Wh en t h e C
h
an
n el 1 sig n al is b ei ng d is p layed, t he
C h a n nel 1
Trigger
sig
n al
is
selecte d as t he internal source .
F or C hannel 2 signal
d
is p
lays, t he C hannel 2 Trigger sig
n
al
is selecte d .
An
ADD VER TICA L M OD E d is p lay causes bot
h pin 5
and p
in
6
of U 317A to b e ΗΙ (see "C h annel Switc h i
ng
L ogic" d
iscussion for
α
description of t h e circuit operation) .
T he sum of t
h
e two c
h annel vertical signals is d is p laye d ,
an d t h e sum of t
he two c h an n el trigger signals is used as t
he
internal trigger
signal .
Summation is accom
p lis hed by t he ΗΙ logic levels from
U 317A pins 5 an
d
6
causing both t he CH 1 Trig and CH 2
Trig signals to go L O .
Wit h t he in p ut transistors to bot
h
Trigger P ic k off Am p
lifiers biase d off, a dd itional circuitry
with in t
h e Trigger P ic k off am p lifiers biases on t
he p ic k off
transistors for b oth C hannel 1 an d C h
annel
2 (see
t h e
C
hannel 1 an dC hannel 2 P ream p lifier circuit d
escriptions .
Α
CH
O P VER TICA L M OD E dis p lay also uses t
h e
s
u m of
t h e two i n ternal trigger signals, bu t t
he switch ing logic
involved is d iffere n t from t
h
e ADD
VER
TICA L
M OD E
d is p lay . Wit h S315 set to C HO
P, α
L O
logic level is applied
to U305 B p in 5 a
n
d to U 305C p
in
9
from t he ΧΥ signal
line via contacts on S315,
S317, and S305 . T h e out p u ts of
bot h U 305C
and U 305B are L O an d are appli ed to the
wire d -AN D
connection on t h e CH 1 Trig and C H 2
Trig
signal lines . T
hese L O signals over r ide t he out p uts from
U315C and U315B to
h ol d t h e in put transistors of both
Ch annel 1 an d Ch
annel
2
Trigger P ic k off Amplifiers biased
off . C h annel 1 and C
h
a
n nel
2
Trigger signals are summe d
as describe d pr
eviously fo r t h e ADD VER TICA L M OD E
dis p lay .
Χ -
Υ
M OD
E . Wh e n t h e
S
E C/DI V switch is set to Χ -
Υ ,
t he C h a n nel 2
signal
is
selecte d as t h e in p ut to t he V ertical
Out put
Amplifier to provide t he Χ -Axis d eflection . T
h
e
C hannel 1
Trigger signal p rovides t h e Χ -Axis signal to t
h
e
ΧΥAm
p lifie r (Diagram 7) via t he Internal
Trigge r
Am p
lifier .
T
h erefore, t he Trigger Switc h ing Logic circ
u it
m u
st
have in p uts t h at ena b le t he C hannel 1
Trigger P ic koff
Am p lifie r .
T he L O logic
level signal su pp lie d by the ΧΥ signal line
to S305 a n d S317 is
removed by switc h ing contacts on t h e
S E C/DI V switch .
Concurrently, α L
O
logic level is place d
on t he ΧΥ signal
line
by
contacts on t he S E C/DI V switch .
T he L O on t h e ΧΥ line is a p
plie d to t he Reset input of
U 317A to select t h e C
h annel
2
sig n
al
for d is p lay . T h is L O
is also app lied to U305B p
in 4
an
d to
U 305D
p in 13 via
U 305A to set up t he Trigger Switc
h ing
L
ogic
t
h
at
enables
t he C hannel 1 Trigger P ic k
off
Am p
lifier .
Α L O on U 305B pin 4 ensures t
h
at t
h
e out pu
t of U 305 B
pin 6 is α L O, w h ic
h
is a pp
lie d to t he C H 1 Trig signal line
to d isable t he C hannel 2
Trigger P ic k off Am p lifier . T h e L O
on U 305D p i n 13 is
gate d to U
315B
p i n 5 . Wit h U315 B
p in 5 L O, t
h
e
out put of U 315 B will be α ΗΙ t h at, w h e n
AN De d wit
h t he ΗΙ p r esent from U 305C p in 8, e n ables t
h e
C
h annel 1 Trigger P ic k off Amplifier .
T R IGG ER
T
he Trigger circuit, s h own on Diagram 4, is
compose d of
t h e Internal
an d E xternal Trigge r Am p lifiers, So
u
rce-
switch ing circuit,
an d Trigger Generator circ u it . Included
in t he Trigger
Generator circuit is t h e Auto Trigger and
Auto Baseline circuitry a
n d t h e
T
V Triggering circuitry .