Maximum input voltage
1 MΩ 300 VRMS with peaks ≤±425 V at the BNC
CAT II
For <100 mV/div, derate at 20 dB/decade above 100 kHz to 30 VRMS at 1 MHz, 10 dB/decade
above 1 MHz
For ≥100 mV/div, derate at 20 dB/decade above 3 MHz to 30 VRMS at 30 MHz, 10 dB/decade
above 30 MHz
50 Ω 5 VRMS with peaks ≤±20 V (DF ≤ 6.25%)
Overvoltage trip is intended to protect against overloads that might damage termination resistors. A
sufficiently large impulse might cause damage regardless of the overvoltage protection circuitry
because of the finite time required to detect and respond.
DC balance 0.1 div with the input DC 50 Ω coupled and 50 Ω terminated
0.2 div at 1 mV/div with the input DC 50 Ω coupled and 50 Ω terminated
0.2 div with the input DC 1 MΩ coupled and 50 Ω terminated
Number of digitized bits 8 bits
Displayed vertically with 25 digitization levels (DL) per division, 10.24 divisions dynamic range.
"DL" is the abbreviation for "digitization level." A DL is the smallest voltage level change that can be
resolved by an 8-bit A-D Converter. This value is also known as the LSB (least significant bit).
Sensitivity range (coarse)
1 MΩ 1 mV/div to 10 V/div in a 1-2-5 sequence
50 Ω 1 mV/div to 1 V/div in a 1-2-5 sequence
Sensitivity range (fine)
1 MΩ
1 mV/div to 5 V/div <–50% to >+50% of selected setting
10 V/div <–50% to 0%
50 Ω
1 mV/div to 500 mV/div <–50% to >+50% of selected setting
1 V/div <–50% to 0%
Allows continuous adjustment from 1 mV/div to
10 V/div
Allows continuous adjustment from 1 mV/div to
1 V/div
Sensitivity resolution (fine) ≤1% of current setting
DC gain accuracy For 50 Ω, 1 MΩ, TPP0500, and TPP1000 path:
±1.5%, derated at 0.100%/°C above 30 °C
±2.0%, derated at 0.100%/°C above 30 °C, 1 mV/Div setting, typical
±3.0% variable gain, derated at 0.100%/°C above 30 °C
Specifications (MSO/DPO5000/B Series) Analog channel input and vertical specification (cont.)
78 MSO70000C/DX, DPO70000C/DX, DPO7000C, MSO5000/B, DPO5000/B Series
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