11
The audio signal obtained from the band pass filter passes through the coupling capacitor C38,
and is lowered in level by the 1/11 attenuator composed of R15 and R14, then is applied to input
pin of PLL decoder IC through C20.
The dividing ratio of R15 and R14 is so set that the PLL decoder IC (IC44) may be locked when the
amplitude of TP-5 exceeds 70 % of the maximum value.
The free-running frequency of PLL is set by the resistor and capacitor connected between pin 14
of IC44 and GND. This free-running frequency may be measured by detecting the output of TP-2
with frequency counter.
The capacitor determines the lock range of PLL, and the larger the capacity, the narrower becomes
the lock range.
Suppose the free-running frequency of PLL is 800 Hz, when the resistance is 56 kohms or higher,
the oscillation stops. Accordingly, the lock range is the maximum when the capacitor is 0.0033 µF
and resistor is 56 kohms.
When the capacitor is 0.0068 µF, the lock range is narrow. In such a case, the free-running fre-
quency must be precisely adjusted to 800 Hz by means of semivariable resistor VR2.
When the PLL is locked, pin 6 of IC44 becomes L level.
3.4 Change of CW transmission speed
The transmission speed of CW is determined by the output frequency of clock generator composed
of IC35, TR1, TR2.
The SPEED slide VR on the front panel is connected to the J9-8 to J9-10 terminals on main PCB.
When the voltage at J9-9 terminal is high (close to J9-10), the oscillation frequency is low, and
when the voltage at J9-9 terminal is low (close to J9-8) , the oscillation frequency is high.
The VR-3 is for adjusting the slow speed, and the VR-4 is for controlling the fast speed. At the time
of manufacture, the variable range of the speed VR is set within 25 characters/minute to 200 cha-
racters/minute (400 Hz to 3200 Hz).
CW monitor sound oscillator
The circuit composed of 3/6 IC21, R45, R46, VR1 and C25 is an 800 Hz monitor sound oscillator of
CW. The frequency is precisely adjusted to 800 Hz by the VR1. The oscillation output is buffered
by the 1/6 IC21 and 2/6 IC43, and is used to drive the driver (2.6 IC34). When pin 15 of IC34 be-
comes L level, the oscillation sound is delivered.
Video output
The video signal to the built-in CRT is controlled in the output level (contrast) by the VR6 in the
main PCB, and is delivered to the CRT unit from the J4-1 terminal.
The horizontal sync and vertical sync signals are delivered separately from the J4-2 and J4-3 to-
ward the CRT unit.
As video signal for external display, composite sync and video signals are respectively shifted in le-
vel by D3 and D4, D5, and applied to the base of TR3, and delivered to the J4-5 as composite vi-
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