TELINK SEMICONDUCTOR TLSR8232 - Demo IR Protocol; IR Timing Design

Telink TLSR8232 BLE SDK Developer Handbook
AN-19112700-E1 182 Ver.1.0.0
As described in Link Layer timing sequence (section 3.2.4), Link Layers uses system
interrupt to process brx event. (In the new SDK, adv event is processed in the main_loop
and does not occupy system interrupt time.) When IR is about to switch PWM output
soon, if brx event related interrupt comes first and occupies MCU time, the time to switch
PWM output may be delayed, thus to result in IR error.
Therefore IR cannot use PWM Normal mode.
For Telink 826x BLE SDK, PWM IR mode is used to implement IR. Please refer to “826x
BLE SDK handbook”.
Since 826x PWM IR mode only supports data pre-storage of two IR FIFOs, if PWM
Signal Frame takes very short time, even shorter than BLE interrupt handling time in
irq_handler, PWM waveform may be delayed, thus it brings a risk for IR mode.
5316 introduces an extra IR DMA FIFO mode which is not supported by 826x. In IR DMA
FIFO mode, since FIFO can be defined in SRAM, more FIFOs are available, which can
effectively solve the shortcoming of PWM IR mode above.
IR DMA FIFO mode supports pre-storage of multiple PWM waveforms into SRAM. Once
DMA is started, no software involvement is needed. This can save frequent SW
processing time, and avoid PWM waveform delay caused by simultaneous response to
multiple IRQs in interrupt system.
Only PWM0 with IR DMA FIFO mode can be used to implement IR. Therefore, in HW
design, IR control GPIO must be PWM0 pin or PWM0_n pin.
10.2.2 Demo IR protocol
The figure below shows demo IR protocol in SDK.
9ms
Start
Data
Repeat Repeat
Data format：Address + Addrss + Command + Command
Red : Start
Blue: Data
Green : Repeat
4.5ms
560uS
560uS
560uS
1690uS
Logical
“0”
Logical “1”
Start
Data
110 mS
110 mS
Repeat
9ms
2250uS
Figure 10-4 Demo IR protocol
10.2.3 IR Timing Design
The figure below shows basic IR timing abased demo IR protocol and feature of IR DMA
FIFO mode.