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TELINK SEMICONDUCTOR TLSR8232 - Page 57

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Telink TLSR8232 BLE SDK Developer Handbook
AN-19112700-E1 56 Ver.1.0.0
Take RX overflow for example, if:
1) The number RX FIFOs is 8;
2) The read pointer and write pointer is 0 and 2 respectively before brx_event(n) is
enabled;
3) main_loop is blocked by task in brx_event(n) and brx_event(n+1) and does not
process RX FIFOs in time;
4) Multiple packets in two brx_event.
As per the description in section 3.2.4.3, BLE packets received during brx_working phase
will only be copied into RX FIFO (RX FIFO write pointer ++), and the operations to fetch
and process data from RX FIFO are implemented in main_loop (RX FIFO read pointer
++). As shown below, the sixth packet will cover the area of rptr (read pointer) 0. It should
be noted that during brx working phase, UI task occupies time slots other than interrupt
handler time for RX, TX, Timer0, etc.
UI task/sleep
UI task
Brx event(n)
brx
post
brx
start
brx working
RX1
TX1
RX2 TX2
Brx event(n+1)
RX3 TX3
RX6 TX6
UI task
brx
post
brx
start
brx working
UI task/sleep
wptr:2
0
1
2
34
5
6
7
rptr:0
RX4 TX4 RX5 TX5
wptr(2+6)&(8-1)=0
0(6)
1
2
3(1)4(2)
5(3)
6(4)
7(5)
rptr:0
If the RX fifo rptr is 0 before the
pkt is received, assuming that
there are multiple pkts in one brx
event and main_loop does not
process RX fifo(means rptr not ++),
then after receiving the 6th RX
data, the RX fifo wptr will cross
the rptr area, causing 1st pkt to
be covered.
Figure 3-11 RX Overflow Case 1
Compared with the extreme case above with long task blockade duration due to one
connection interval, the case below is more likely to occur.
During one brx_event, since master writes multiple packets into slave, like 7 or 8 packets,
slave fails to process these packets in time. As shown below, the rptr (read pointer) is
increased by two, but the wptr (write pointer) is also increased by eight, which thus
causes data overflow.

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