Terasic DE1-SOC User Manual

DE1-SoC User Manual
1
www.terasic.com
August 5, 2015
i3

Terasic DE1-SOC Specifications

General

FPGA Max. Memory	4, 450 Kbits
Processor	Dual-core ARM Cortex-A9 (HPS)
Ethernet	10/100/1000 Mbps
Switches	4
Push-buttons	4
HSMC (High-Speed Mezzanine Connector)	1
On-board USB Blaster	Yes
Clock Frequency	50 MHz
Storage	MicroSD Card Slot
FPGA	Altera Cyclone V SoC (5CSEMA5F31C6)
Memory	1GB DDR3
USB	USB Host
HDMI	HDMI
Audio	24-bit CODEC, Line-in, Line-out, Microphone
ADC	12-bit ADC
Serial	UART
Video	VGA, HDMI
Power Supply	5V

Summary

DE1-SoC Development Kit Overview

DE1-SoC Package Contents

Details the hardware and accessories included in the DE1-SoC Development Kit.

DE1-SoC System CD Contents

Describes the contents of the DE1-SoC System CD, including manuals and designs.

Getting Technical Assistance

Provides contact information and resources for obtaining technical assistance.

Introduction to the DE1-SoC Board

DE1-SoC Board Layout and Components

Illustrates the physical layout and identifies key components on the DE1-SoC board.

DE1-SoC Board Block Diagram

Presents a high-level block diagram showing the interconnections of the board's subsystems.

Using the DE1-SoC Board

FPGA Configuration Mode Settings

Explains how to select the FPGA configuration scheme using DIP switches.

Cyclone V SoC FPGA Configuration

Details the methods for programming the Cyclone V SoC FPGA via JTAG and AS modes.

Board Status Indicators

Describes the LEDs and indicators that display the board's operational status.

Board Reset Mechanisms

Explains the function of the HPS cold and warm reset buttons.

Clock Circuitry Details

Details the clock sources and distribution on the DE1-SoC board.

FPGA Peripherals

Introduces peripherals directly connected to the FPGA fabric.

User Push-buttons, Switches, and LEDs

Covers the functionality and pin assignments of user push-buttons, switches, and LEDs.

7-segment Displays

Details the six 7-segment displays and their FPGA pin assignments for output.

2x20 GPIO Expansion Headers

Describes the 2x20 GPIO headers for board expansion and their pin assignments.

24-bit Audio CODEC

Explains the 24-bit audio CODEC, its features, and connections.

I2C Multiplexer Functionality

Details the I2C multiplexer used for accessing peripherals.

VGA Output Interface

Describes the VGA output interface, its DAC, and timing specifications.

TV Decoder for Video Input

Explains the TV decoder chip for video input and its interface.

Infrared Receiver Module

Describes the infrared receiver module and its connection to the FPGA.

Infrared Emitter LED

Details the infrared emitter LED and its connection to the FPGA.

SDRAM Memory Module

Covers the 64MB SDRAM memory module and its pin assignments.

PS/2 Serial Port Interface

Explains the PS/2 interface for keyboard/mouse input and its pin assignments.

A/D Converter and 2x5 Header

Details the 8-channel 12-bit ADC and its 2x5 header connections.

HPS Peripherals Overview

Introduces peripherals connected to the HPS section of the SoC.

HPS User Push-buttons and LEDs

Describes HPS-specific user push-buttons and LEDs and their control.

Gigabit Ethernet Interface

Explains the Gigabit Ethernet PHY and its connection and status LEDs.

UART Communication via USB

Details the UART interface for HPS communication via USB.

HPS DDR3 Memory

Covers the 1GB DDR3 SDRAM connected to the HPS and its pin assignments.

Micro SD Card Socket Functionality

Explains the Micro SD card interface for storage and booting.

2-port USB Host Interface

Describes the USB 2.0 host ports and their interface controller.

G-sensor Module

Details the G-sensor module, its I2C interface, and connections.

LTC Connector for Daughter Cards

Explains the 14-pin LTC connector for Linear Technology daughter cards.

DE1-SoC System Builder Tool

Introduction to System Builder

Introduces the DE1-SoC System Builder tool for creating Quartus II projects.

System Builder Design Flow

Outlines the steps involved in using the DE1-SoC System Builder tool.

Using the DE1-SoC System Builder

Provides detailed instructions on how to operate the DE1-SoC System Builder utility.

FPGA Examples and Demonstrations

DE1-SoC Factory Configuration Demo

Demonstrates the default factory configuration of the DE1-SoC board.

Audio Recording and Playing Example

Shows how to implement audio recording and playback using the CODEC.

Karaoke Machine Example

Details how to create a Karaoke machine using audio ports and the CODEC.

SDRAM Test in Nios II

Illustrates SDRAM access and verification using Nios II processor.

SDRAM Test in Verilog HDL

Demonstrates SDRAM testing using Verilog HDL and a system controller.

TV Box Demonstration

Explains how to turn the board into a TV box using video and audio peripherals.

PS/2 Mouse Demonstration

Shows how to implement bi-directional communication with a PS/2 mouse.

IR Emitter LED and Receiver Demo

Demonstrates the use of IR emitter LED and IR receiver for communication.

ADC Reading Demonstration

Illustrates the performance evaluation of the 8-channel 12-bit A/D Converter.

HPS SoC Examples and Demonstrations

HPS Hello World Program

Guides on developing the first HPS program using Altera SoC EDS tool.

HPS Users LED and KEY Control

Shows how to control user LEDs and keys via HPS GPIO controller.

I2C Interfaced G-sensor with HPS

Explains how to control the G-sensor using the HPS I2C driver.

HPS I2C Multiplexer Test

Demonstrates switching the I2C multiplexer for HPS to access the I2C bus.

HPS SoC and FPGA Integrated Examples

HPS Control of FPGA LED and HEX

Shows how HPS controls FPGA LEDs and HEX displays via Lightweight HPS-to-FPGA Bridge.

DE1-SoC Control Panel GUI Example

Demonstrates controlling HPS/FPGA peripherals and GUI programming on Linux.

DE1-SoC Linux Frame Buffer Project

Utilizes VGA as a standard output for Linux OS with frame buffer project.

Programming the EPCS Configuration Device

Pre-Programming Setup

Sets up the FPGA for programming the quad Flash configuration device.

Convert SOF to JIC File

Details the process of converting a .SOF file to a .JIC file in Quartus II.

Write JIC File to EPCS Device

Explains how to program the EPCS device using a created .JIC file.

Erase EPCS Device Contents

Describes the steps to erase existing files from the EPCS device.

Nios II Boot from EPCS (Quartus II v13.1)

Provides guidance on booting from EPCS using Quartus II software.

Appendix Information

Manual Revision History

Lists the changes and updates made in different versions of the manual.

Copyright and Legal Notices

Contains the copyright information and legal notices for the manual.