Texas Instruments MSP430 series - Page 36

MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547I –JUNE 2007–REVISED DECEMBER 2012 www.ti.com
Outputs (Ports P1, P2, P3, P4, P5, P6)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
I
OH(max)
= -1.5 mA
(1)
V
CC
- 0.25 V
CC
2.2 V
I
OH(max)
= -6 mA
(2)
V
CC
- 0.6 V
CC
V
OH
High-level output voltage V
I
OH(max)
= -1.5 mA
(1)
V
CC
- 0.25 V
CC
3 V
I
OH(max)
= -6 mA
(2)
V
CC
- 0.6 V
CC
I
OL(max)
= 1.5 mA
(1)
V
SS
V
SS
+ 0.25
2.2 V
I
OL(max)
= 6 mA
(2)
V
SS
V
SS
+ 0.6
V
OL
Low-level output voltage V
I
OL(max)
= 1.5 mA
(1)
V
SS
V
SS
+ 0.25
3 V
I
OL(max)
= 6 mA
(2)
V
SS
V
SS
+ 0.6
(1) The maximum total current, I
OH(max)
and I
OL(max)
, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I
OH(max)
and I
OL(max)
, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports P1, P2, P3, P4, P5, P6)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Port output 2.2 V DC 10
f
Px.y
frequency with P1.4/SMCLK, C
L
= 20 pF, R
L
= 1 kΩ
(1)(2)
MHz
3 V DC 12
load
2.2 V DC 12
Clock output
f
Port°CLK
P2.0/ACLK/CA2, P1.4/SMCLK, C
L
= 20 pF
(2)
MHz
frequency
3 V DC 16
P1.0/TACLK/CAOUT, C
L
= 20 pF, LF mode 30% 50% 70%
P1.0/TACLK/CAOUT, C
L
= 20 pF, XT1 mode 40% 50% 60%
P1.1/TA0, C
L
= 20 pF, XT1 mode 40% 60%
Duty cycle of
t
(Xdc)
output frequency
P1.1/TA0, C
L
= 20 pF, DCO 50% – 15 ns 50% 50% + 15 ns
P1.4/SMCLK, C
L
= 20 pF, XT2 mode 40% 60%
P1.4/SMCLK, C
L
= 20 pF, DCO 50% – 15 ns 50% + 15 ns
(1) A resistive divider with two 0.5-kΩ resistors between V
CC
and V
SS
is used as load. The output is connected to the center tap of the
divider.
(2) The output voltage reaches at least 10% and 90% V
CC
at the specified toggle frequency.
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