Texas Instruments TMS320 DSP User Manual (English)

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4.1.2 Stack Memory

4.1.3 Static Local and Global Data Memory

Data Memory

In the example above, the algorithm requires 960 16-bit words of single-access on-chip memory, 720

16-bit words of external persistent memory, and there are no special alignment requirements for this

memory. Note that the entries in this table are not required to be constants; they may be functions of

algorithm instance creation parameters.

In addition to bulk "heap" memory, algorithms often make use of the stack for very efficient allocation of

temporary storage. For most real-time systems, the total amount of stack memory for a thread is set once

(either when the program is built or when the thread is created) and never changes during execution of

the thread. This is done to ensure deterministic execution of the thread. It is important, therefore, that the

system integrator know the worst-case stack space requirements for every algorithm.

Rule 20

All algorithms must characterize their worst-case stack space memory requirements (including

alignment).

Stack space requirements for an algorithm must be characterized using a table such as that shown below.

Size Align

Stack Space 400 0

Both the size and alignment fields should be expressed in units of 8-bit bytes. If no special alignment is

required, the alignment number should be set to zero.

In the example above, the algorithm requires 200 16-bit words of stack memory and there is no special

alignment requirement for this memory. Note that the entry in this table are not required to be a constant;

it may be function of the algorithm's instance creation parameters.

One way to achieve reentrancy in a function is to declare all scratch data objects on the local stack. If the

stack is in on-chip memory this provides easy access to fast scratch memory.

The problem with this approach to reentrancy is that, if carried too far, it may require a very large stack.

While this is not a problem for single threaded applications, traditional multi-threaded applications must

allocate a separate stack for each thread. It is unlikely that more than a few these stacks will fit in on-chip

memory. Moreover, even in a single threaded environment, an algorithm has no control over the

placement of the system stack; it may end up with easy access to very slow memory.

These problems can be avoided by algorithms taking advantage of the IALG interface to declare their

scratch data memory requirements. This gives the application the chance to decide whether to allocate

the memory from the stack or the heap, which ever is best for the system overall.

Guideline 5

Algorithms should keep stack size requirements to a minimum.

Static data memory is any data memory that is allocated and placed when the program is built and

remains fixed during program execution. In many DSP architectures, there are special instructions that

can be used to access static data very efficiently by encoding the address of the data in the instruction's

opcode. Therefore, once the program is built, this memory cannot be moved.

Rule 21

Algorithms must characterize their static data memory requirements.

SPRU352G – June 2005 – Revised February 2007 Algorithm Performance Characterization 39

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Texas Instruments TMS320 DSP Specifications

General

Category	Digital Signal Processor
Manufacturer	Texas Instruments
Data Bus Width	Varies by model (e.g., 16-bit, 32-bit)
Architecture	Harvard architecture
Address Bus Width	Varies by model
Memory	Varies by model
On-Chip RAM	Varies by model
On-Chip ROM	Varies by model
Applications	Audio processing, telecommunications
Operating Temperature	Varies by model
Package Type	Varies by model (e.g., QFP, BGA)