Texas Instruments TMS320 DSP User Manual

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V
X = 0ld
Y = new
VX
L2 cache External memory
Y
DMA
Cache line
6.14 C55x Specific DMA Rules and Guidelines
6.14.1 Supporting Packed/Burst Mode DMA Transfers
C55x Specific DMA Rules and Guidelines
DMA Rule 7 is a rule for the client application writer. For external memory buffers that are acquired using
DMA transfers, the corresponding cache entries must be invalidated to ensure that they are not cached.
For buffers that are modified using CPU accesses, the corresponding cache entries must first be written
back to external memory and then invalidated to ensure cache coherency.
It is also important that these buffers are allocated on a cache line boundary and be a multiple of cache
lines in size. As shown in Section 6.13.4 , if for some location x that is accessed by the DMA, there is other
data v sharing the same cache line, the entire cache line may be brought into the cache when v is
accessed. Location x would then end up in the cache, which violates the purpose of DMA Rule 6.
DMA Rule 8
For C6000 algorithms, all buffers residing in external memory involved in a DMA transfer should be
allocated on a cache line boundary and be a multiple of the cache line length in size.
DMA Rule 8 is added for algorithm writers who divide buffers supplied to them through their function
interface into smaller buffers, and then use these smaller buffers in DMA transfers. In this case, the
transfer must also occur on buffers aligned on a cache line boundary. Note that this does not mean the
transfer size needs to be a multiple of the cache line length in size. Instead, the "buffer" containing
memory locations involved in the transfer must be considered a single buffer; the algorithm must not
directly access part of the buffer as per DMA Rule 6.
DMA Rule 9
C6000 Algorithms should not use stack allocated buffers as the source or destination of any DMA
transfer.
DMA Rule 9 is necessary since buffers allocated on the stack are not aligned on cache line boundaries,
and there is no mechanism to force alignment. Furthermore, this rule is good practice, as it helps to
minimize an algorithm's stack size requirements.
Due to the performance requirements of certain C55x and OMAP platforms, DMA transfers must use
burst-enabled/packed transfer modes as much as possible. The basic problem is that if the source or
destination addresses are not aligned on a burst boundary, then the burst mode gets disabled by
hardware. DMA Guideline 4 is introduced to transparently assist ACPY2 library implementations on the
C55x platforms to operate in burst-enabled/packed mode.
DMA Guideline 4
To facilitate high performance, C55x algorithms should request DMA transfers with source and
destinations aligned on 32-bit byte addresses.
Use of the DMA Resource70 SPRU352G – June 2005 – Revised February 2007
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Texas Instruments TMS320 DSP Specifications

General

Category	Digital Signal Processor
Manufacturer	Texas Instruments
Data Bus Width	Varies by model (e.g., 16-bit, 32-bit)
Architecture	Harvard architecture
Address Bus Width	Varies by model
Memory	Varies by model
On-Chip RAM	Varies by model
On-Chip ROM	Varies by model
Applications	Audio processing, telecommunications
Operating Temperature	Varies by model
Package Type	Varies by model (e.g., QFP, BGA)

Summary

Preface

Read This First

Provides introductory information and context for the document.

Overview

Scope of the Standard

Defines the levels of guidelines for the TMS320 DSP Algorithm Standard.

Requirements of the Standard

Lists key elements and objectives for the TMS320 DSP Algorithm Standard.

Goals of the Standard

Outlines the objectives for creating and adhering to the TMS320 DSP Algorithm Standard.

Intentional Omissions

Lists aspects intentionally omitted from the current version of the standard.

System Architecture

Describes the common partitioning of modern DSP system architectures.

General Programming Guidelines

Use of C Language

Specifies adherence to C language run-time conventions for algorithm interoperability.

Threads and Reentrancy

Defines threads and discusses reentrancy requirements for algorithms.

Data Memory

Discusses memory allocation, types, and management for algorithms.

Program Memory

Covers requirements for code relocation and alignment in program memory.

ROM-ability

Addresses the ability of algorithm code to be placed in ROM.

Use of Peripherals

Prohibits direct peripheral access and outlines how algorithms can use DMA.

Algorithm Component Model

Interfaces and Modules

Describes modules as the basic software component and their interfaces.

Algorithms

Defines algorithms as modules implementing the IALG interface.

Packaging

Details how to bundle modules into a deliverable form for development systems.

Algorithm Performance Characterization

Data Memory

Characterizes algorithm data memory requirements (heap, stack, static).

Program Memory

Details requirements for characterizing algorithm program memory usage.

Interrupt Latency

Specifies how to characterize and limit worst-case interrupt latency.

Execution Time

Explains how to characterize typical and worst-case execution times for algorithms.

DSP-Specific Guidelines

CPU Register Types

Categorizes CPU registers and provides guidelines for their use.

Use of Floating Point

Advises against the use of floating-point data types to reduce library dependencies.

TMS320C6xxx Rules and Guidelines

Provides specific rules and guidelines for TMS320C6000 family DSPs.

TMS320C54xx Rules and Guidelines

Provides specific rules and guidelines for TMS320C5400 family DSPs.

TMS320C55x Rules and Guidelines

Provides specific rules and guidelines for TMS320C5500 family DSPs.

TMS320C24xx Guidelines

Provides specific rules and guidelines for TMS320C24xx family DSPs.

TMS320C28x Rules and Guidelines

Provides specific rules and guidelines for TMS320C28x family DSPs.

Use of the DMA Resource

Overview

Introduces rules and guidelines for algorithms utilizing DMA resources.

Algorithm and Framework

Defines the relationship between algorithms and frameworks for DMA resource management.

Requirements for the Use of the DMA Resource

Lists requirements for DMA usage in eXpressDSP-compliant algorithms.

Logical Channel

Explains the concept of logical DMA channels for algorithm use.

Data Transfer Properties

Defines parameters for DMA transfer blocks (frames, elements).

Data Transfer Synchronization

Discusses methods to ensure DMA transfers complete before CPU access.

Abstract Interface

Describes the IDMA2/IDMA3 interfaces for declaring DMA resource requirements.

Resource Characterization

Details how to characterize DMA resource usage (concurrency, size, frequency).

Runtime APIs

Lists allowed runtime APIs for configuring and managing DMA transfers.

Strong Ordering of DMA Transfer Requests

Explains FIFO ordering and queue ID properties for DMA transfers.

Submitting DMA Transfer Requests

Describes functions for submitting DMA transfer requests and their alignment requirements.

Device Independent DMA Optimization Guideline

Provides a guideline to minimize DMA channel reconfiguration overhead.

C6xxx Specific DMA Rules and Guidelines

Covers DMA rules and guidelines specific to C6000 series DSPs.

C55x Specific DMA Rules and Guidelines

Covers DMA rules and guidelines specific to C55x series DSPs.

Inter-Algorithm Synchronization

Discusses sharing physical DMA channels between algorithms.

Rules and Guidelines

General Rules

Enforces rules for eXpressDSP-compliant software and identifies guideline types.

Performance Characterization Rules

Lists rules related to characterizing algorithm performance metrics.

DMA Rules

Lists rules specifically for algorithms utilizing the DMA resource.

General Guidelines

Lists general recommendations for algorithm development.

DMA Guidelines

Lists guidelines related to DMA usage by algorithms.

Core Run-Time APIs

TI C-Language Run-Time Support Library

Lists allowable TI C-language run-time support library functions for algorithms.

DSP/BIOS Run-time Support Library

Lists allowable DSP/BIOS run-time support functions for algorithms.

Bibliography

Glossary

Glossary of Terms

Defines key terms used throughout the TMS320 DSP Algorithm Standard document.