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General| Category | Digital Signal Processor |
|---|---|
| Manufacturer | Texas Instruments |
| Data Bus Width | Varies by model (e.g., 16-bit, 32-bit) |
| Architecture | Harvard architecture |
| Address Bus Width | Varies by model |
| Memory | Varies by model |
| On-Chip RAM | Varies by model |
| On-Chip ROM | Varies by model |
| Applications | Audio processing, telecommunications |
| Operating Temperature | Varies by model |
| Package Type | Varies by model (e.g., QFP, BGA) |
Provides introductory information and context for the document.
Defines the levels of guidelines for the TMS320 DSP Algorithm Standard.
Lists key elements and objectives for the TMS320 DSP Algorithm Standard.
Outlines the objectives for creating and adhering to the TMS320 DSP Algorithm Standard.
Lists aspects intentionally omitted from the current version of the standard.
Describes the common partitioning of modern DSP system architectures.
Specifies adherence to C language run-time conventions for algorithm interoperability.
Defines threads and discusses reentrancy requirements for algorithms.
Discusses memory allocation, types, and management for algorithms.
Covers requirements for code relocation and alignment in program memory.
Addresses the ability of algorithm code to be placed in ROM.
Prohibits direct peripheral access and outlines how algorithms can use DMA.
Describes modules as the basic software component and their interfaces.
Defines algorithms as modules implementing the IALG interface.
Details how to bundle modules into a deliverable form for development systems.
Characterizes algorithm data memory requirements (heap, stack, static).
Details requirements for characterizing algorithm program memory usage.
Specifies how to characterize and limit worst-case interrupt latency.
Explains how to characterize typical and worst-case execution times for algorithms.
Categorizes CPU registers and provides guidelines for their use.
Advises against the use of floating-point data types to reduce library dependencies.
Provides specific rules and guidelines for TMS320C6000 family DSPs.
Provides specific rules and guidelines for TMS320C5400 family DSPs.
Provides specific rules and guidelines for TMS320C5500 family DSPs.
Provides specific rules and guidelines for TMS320C24xx family DSPs.
Provides specific rules and guidelines for TMS320C28x family DSPs.
Introduces rules and guidelines for algorithms utilizing DMA resources.
Defines the relationship between algorithms and frameworks for DMA resource management.
Lists requirements for DMA usage in eXpressDSP-compliant algorithms.
Explains the concept of logical DMA channels for algorithm use.
Defines parameters for DMA transfer blocks (frames, elements).
Discusses methods to ensure DMA transfers complete before CPU access.
Describes the IDMA2/IDMA3 interfaces for declaring DMA resource requirements.
Details how to characterize DMA resource usage (concurrency, size, frequency).
Lists allowed runtime APIs for configuring and managing DMA transfers.
Explains FIFO ordering and queue ID properties for DMA transfers.
Describes functions for submitting DMA transfer requests and their alignment requirements.
Provides a guideline to minimize DMA channel reconfiguration overhead.
Covers DMA rules and guidelines specific to C6000 series DSPs.
Covers DMA rules and guidelines specific to C55x series DSPs.
Discusses sharing physical DMA channels between algorithms.
Enforces rules for eXpressDSP-compliant software and identifies guideline types.
Lists rules related to characterizing algorithm performance metrics.
Lists rules specifically for algorithms utilizing the DMA resource.
Lists general recommendations for algorithm development.
Lists guidelines related to DMA usage by algorithms.
Lists allowable TI C-language run-time support library functions for algorithms.
Lists allowable DSP/BIOS run-time support functions for algorithms.
Defines key terms used throughout the TMS320 DSP Algorithm Standard document.
