5.5.3 Program Models
5.5.4 Relocatability
TMS320C55x Rules and Guidelines
Rule 32
All C55x algorithms must access all static and global data as far data; also, the algorithms should be
instantiable in a large memory model.
Only the large memory model is supported for the program memory. So there are no special program
memory requirements for this processor. Just to reemphasize the point, all the program code must be
completely relocatable and must not necessarily require placement in on-chip memory.
Rule 33
C55x algorithms must never assume placement in on-chip program memory; i.e., they must properly
operate with program memory operated in instruction cache mode.
The above rule can be interpreted as to the algorithm code must not have any assumptions on the timing
information to guarantee the functionality.
Some of the C55X devices have a constraint that the data accessed with the B-bus (coefficient
addressing) must come from on-chip memory. The data that is accessed by B-bus can be static-data or
heap-data. All C55x algorithms that access data (static or heap) with the B-bus must adhere to the
following rule.
Rule 34
All C55x algorithms that access data by B-bus must document:
• the instance number of the IALG_MemRec structure that is accessed by the B-bus (heap-data),
and
• the data-section name that is accessed by the B-bus (static-data).
Example 1
Int algAlloc(IALG_Params *algParams,
IALG_Fxns **p,
IALG_MemRec memTab[])
{
EncoderParams *params = (EncoderParams *)algParams;
If (params == NULL) {
params = &ENCODERATTRS;
}
memTab[0].size = sizeof (EncoderObj);
...
memTab[1].size = params->frameDuration * 8 * sizeof(int);
...
memTab[3].size = params->sizeInBytes;
...
return (2);
}
Suppose, in the above example, the memTab[1] and memTab[3] are accessed by the B-bus. Then this
must be documented as per the Rule 34 as follows:
Number of memTab blocks that are accessed by B-bus Block numbers
2 1,3
SPRU352G – June 2005 – Revised February 2007 DSP-Specific Guidelines 53
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