TYAN S8050 - Page 104

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104
3.5.2.1 CPU Common Options Submenu
CCD/Core/Thread Enablement
CCD/Core/Thread Enablement settings
Prefetcher settings
Prefetcher parameters
Platform First Error Handling
Enable/disable PFEH, cloak individual banks, and mask deferred error interrupts
from each bank.
Enabled / Disabled / Auto
Core Performance Boost
Disable CPB
Disabled / Auto
Global C-state Control
Controls IO based C-state generation and DF C-states.
Disabled / Enabled / Auto