TYAN S8050 - Page 115

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115
DRAM Corrected Error Counter Enable
Configure DRAM Corrected Error Counter function. Only meaningful when
PcdAmdCcxCfgPFEHEnable is TRUE.
Disabled / NoLeakMode / LeakMode
DRAM Corrected Error Counter Interleaving
Enable SMI when DRAM Corrected Error Counter count exceeds the threshold
value.
False / True
DRAM Corrected Error Counter Leak
Program Rate value for DRAM Corrected Error Counter function. Only meaningful
when PcdAmdDdrEccErrorCounterEnable is set to LeakMode(Value:0x00-0x1F).
7
DRAM Corrected Error Counter Start
Program starting count value for DRAM Corrected Error Counter function. Only
meaningful when PcdAmdDdrEccErrorCounterEnable is not Disable(0x00 –
0xFFFF).
FFFF5