SARA-G3 series - System Integration Manual
UBX-13000995 - R06 Objective Specification Design-in
Page 159 of 218
ETSI EN 301 489-1
[16]), to satisfy the requirements for ESD immunity test summarized in Table
38Table 38.
Antenna interface
The ANT pin of SARA-G3 series modules provides ESD immunity up to ±4 kV for direct Contact
Discharge and up to ±8 kV for Air Discharge: no further precaution to ESD immunity test is needed, as
implemented in the EMC / ESD approved reference design of SARA-G3 series modules.
The antenna interface application circuit implemented in the EMC / ESD approved reference designs of
SARA-G3 series modules is described in Figure 40Figure 40 in case of antenna detection circuit not
implemented, and is described in Figure 41Figure 41 and Table 22Table 22 in case of antenna detection
circuit implemented (section 2.3).
RESET_N pin
The following precautions are suggested for the RESET_N line of SARA-G3 series modules, depending on
the application board handling, to satisfy ESD immunity test requirements:
It is recommended to keep the connection line to RESET_N as short as possible
Maximum ESD sensitivity rating of the RESET_N pin is 1 kV (Human Body Model according to JESD22-
A114). Higher protection level could be required if the RESET_N pin is externally accessible on the
application board. The following precautions are suggested to achieve higher protection level:
A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS
CT0402S14AHSG varistor) should be mounted on the RESET_N line, close to accessible point
The RESET_N application circuit implemented in the EMC / ESD approved reference designs of SARA-G3
series modules is described in Figure 34Figure 34 and Table 20Table 20 (section 2.2.2).
SIM interface
The following precautions are suggested for SARA-G3 series modules SIM interface (VSIM, SIM_RST,
SIM_IO, SIM_CLK pins), depending on the application board handling, to satisfy ESD immunity test
requirements:
A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470J) must be mounted on the lines connected
to VSIM, SIM_RST, SIM_IO and SIM_CLK pins to assure SIM interface functionality when an
electrostatic discharge is applied to the application board enclosure
It is suggested to use as short as possible connection lines at SIM pins
Maximum ESD sensitivity rating of SIM interface pins is 1 kV (Human Body Model according to JESD22-
A114). Higher protection level could be required if SIM interface pins are externally accessible on the
application board. The following precautions are suggested to achieve higher protection level:
A low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Tyco Electronics PESD0402-
140) should be mounted on each SIM interface line, close to accessible points (i.e. close to the
SIM card holder)
The SIM interface application circuit implemented in the EMC / ESD approved reference designs of
SARA-G3 series modules is described in Figure 45Figure 45 and Table 25Table 25 (section 2.4).
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