ZED-F9P-Integration manual
4 Design
This section provides information to help carry out a successful schematic and PCB design
integrating the ZED-F9P.
Do not load Pin 4 (ANT_DETECT) with a capacitance more than 1 nF.
4.1 Pin assignment
The pin assignment of the ZED-F9P module is shown in Figure 34. The defined configuration of the
PIOs is listed in Table 30.
The ZED-F9P is an LGA package with the I/O on the outside edge and central ground pads.
Figure 34: ZED-F9P pin assignment
Pin No Name I/O Description
1 GND - Ground
2 RF_IN I RF input
3 GND - Ground
4 ANT_DETECT I Active antenna detect - default active high
5 ANT_OFF O External LNA disable - default active high
6 ANT_SHORT_N I Active antenna short detect - default active low
7 VCC_RF O Voltage for external LNA
8 Reserved - Reserved
UBX-18010802 - R08
4 Design Page 71 of 110
Early production information
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