Ublox NINA-B3 Series - Serial Peripheral Interface (SPI); Quad Serial Peripheral Interface (QSPI)

NINA-B3 series - System integration manual
UBX-17056748 - R13 System description Page 11 of 72
C1-Public
The UART can be used as both a 4-wire UART with hardware flow control and a 2-wire UART with only
TXD and RXD. If using the UART in 2-wire mode, CTS should be connected to GND on the
NINA-B3 module.
Depending on the bootloader used, the UART interface can also be used for software upgrades. See
also Software.
The u-connectXpress software adds the DSR and DTR pins to the UART interface. These pins are not
used as originally intended, but to control the state of the NINA-B3 module. Depending on the current
configuration, the DSR can be used to:
• Enter command mode
• Disconnect and/or toggle connectable status
• Enable/disable the rest of the UART interface
• Enter/wake up from the sleep mode
See the NINA-B3 series data sheet [2] for characteristics information about the UART interface.
Interface
Default configuration
COM port
115200 baud, 8 data bits, no parity, 1 stop bit, hardware flow control
Table 3: Default settings for the COM port while using the u-connectXpress software
It is recommended to make the UART available either as test points or connected to a header for a
software upgrade.
The I/O level of the UART will follow the VCC voltage and it can thus be in the range of 1.8 V and 3.6 V.
If you are connecting the NINA-B3 module to a host with a different voltage on the UART interface, a
level shifter should be used.
1.7.2 Serial Peripheral Interface (SPI)
NINA-B3 supports up to three serial peripheral interfaces that can operate in both master and slave
modes with a maximum serial clock frequency of 8 MHz in both these modes. The SPI interfaces use
the following signals:
• SCLK
• MOSI
• MISO
• CS
• DCX (Data/Command signal). This signal is optional but is sometimes used by the SPI slaves to
distinguish between SPI commands and data.
When using the SPI interface in master mode, it is possible to use GPIOs as additional Chip Select (CS)
signals to allow addressing of multiple slaves.
1.7.3 Quad serial peripheral interface (QSPI)
The Quad Serial Peripheral Interface enables connection of external memory to the NINA-B3 module
in order to increase the application program size. The QSPI uses the following signals:
• CLK, serial clock output, up to 32 MHz
• CS, Chip/Slave select output, active low, selects which slave on the bus to talk to
• D0, MOSI serial output data in single mode, data I/O signal in dual/quad mode
• D1, MISO serial input data in single mode, data I/O signal in dual/quad mode
• D2, data I/O signal in quad mode (optional)
• D3, data I/O signal in quad mode (optional)