NINA-W1 series - System integration manual
UBX-17005730 - R11 System description Page 11 of 55
C1 - Public
Typical UART interface characteristics are described in data sheet references [2], [3] and [4] .
Interface Default configuration
UART interface 11520 baud, 8 data bits, no parity, 1 stop bit, and hardware flow control
Table 2: UART port default settings
It is recommended that the UART is either connected to a header for firmware upgrade or made
available for test points.
The IO level of the UART follows VCC_IO.
1.7.2 Ethernet (RMII+SMI)
⚠ NINA-W13 only supports Reduced Media-independent Interface (RMII) from software version
2.0.0 onwards.
NINA-W1 series modules include a full RMII for Ethernet MAC to PHY communication over the Station
Management Interface (SMI). RMII and SMI use nine signals in total. The RMII and SMI interfaces
require an external 50 MHz clock source either from a compatible PHY chip or from an external
oscillator.
The two-wire SMI is used to configure the PHY chip. It uses a clock line and a data line to setup the
internal registers on PHY chip.
The pin multiplexing of the RMII interface imposes limitations in the functionality of NINA-W13/W15
series module when using the interface. The following functions are turned off when RMII
communication is initiated:
• Red, Green and Blue LEDs are disabled
• UART is run without flow control as CTS and RTS functionality is disabled
• DSR and DTR functionality is disabled
A 1.5 kΩ pull up resistor must be added to MDIO pin.
1.7.2.1 Startup precautions
To ensure that the boot mode is not entered inadvertently, the RMII_CLK input (GPIO27) is
multiplexed with the ESP boot pin and must be held high 1.2 ms after the reset signal is released.
EVK-NINA-W1 uses two buffers and a low pass filter to delay the reset signal going to the PHY circuit,
as shown in Figure 4.
This delays the clock so that it starts a short time after the module is released from reset.
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