Ublox NINA-W1 Series System Integration Manual

NINA-W1 series - System integration manual
UBX-17005730 - R11 System description Page 8 of 55
C1 - Public
* Only on NINA-W152 and NINA-W152
** Only on NINA-W156. Support in u-connectXpress - pending implementation
Figure 3: NINA-W15 series block diagram
1.3 CPU
NINA-W1 series modules use a dual-core system that includes two Harvard Architecture Xtensa LX6
CPUs with maximum 240 MHz internal clock frequency. The internal memory of NINA-W1 supports:
• 448 kB ROM for booting and core functions
• 520 kB SRAM for data and instruction
• 16 or 32 Mbit FLASH memory for code storage, including hardware encryption to protect
programs and data.
• 1 kbit EFUSE (non- erasable memory) for MAC addresses, module configuration, flash-
encryption, and Chip-ID.
Open CPU variants (NINA-W10) also support external FLASH and SRAM memory through a Quad SPI
interface.
1.4 Operating modes
1.4.1 Power modes
NINA-W1 series modules are power efficient devices capable of operating in different power saving
modes and configurations. Different sections of the modules can be powered off when they are not
needed, and complex wake up events can be generated from different external and internal inputs.
For the lowest current consumption modes an external LPO clock is required (interface available for
NINA-W10 series modules and NINA-W156).
Flash (16 Mbit)
Linear voltage regulators
RF
ROM
Wi-Fi
baseband
IO Buffers
2xXtensa 32-bit LX6 MCU
SRAM (4Mbit)
Cryptographic
hardware
accelerations
PIFA antenna
(NINA-W152)
PLL
Quad SPI
VCC_IO
VCC (3.0
-3.6V)
40 MHz
Reset
UART
RMII
EFUSE
GPIO
BPF*
(NINA-W15
1)
ANT
Wi-Fi
baseband
(NINA-W156)
PIFA antenna
SPI
LPO*
*

Ublox NINA-W1 Series Specifications

General

Brand	Ublox
Model	NINA-W1 Series
Category	Wireless Router
Language	English