Ublox NINA-W106 - Data interfaces

NINA-W1 series - System integration manual
UBX-17005730 - R11 System description Page 7 of 55
C1 - Public
1.2 Architecture
1.2.1 Block diagrams
Figure 1: NINA-W13 series block diagram
* Only on NINA-W101 and NINA-W102.
** 16Mbit
NINA-W101 and NINA-W102; 32Mbit NINA-W106.
Figure 2: NINA-W10 series block diagram
Flash (16 Mbit)
Linear voltage regulators
RF
ROM
Wi-Fi
baseband
IO Buffers
2xXtensa 32-bit LX6 MCU
SRAM (4Mbit)
Cryptographic
hardware
accelerations
PIFA antenna
(NINA-W132)
PLL
Quad SPI
VCC_IO
VCC (3.0
-3.6V)
40 MHz
Reset
UART
RMII
EFUSE
GPIO
BPF
(NINA-
W131)
ANT
Linear voltage regulators
RF
ROM
Wi-Fi
baseband
Bluetooth
Baseband
IO Buffers
2xXtensa 32-bit LX6 MCU
SRAM (4Mbit)
Cryptographic
hardware
accelerations
PIFA antenna
(NINA-W102)
PLL
VCC_IO
VCC (3.0- 3.6V)
40 MHz
Reset
ANT
UART
RMII
I2C
SPI
SDIO
Quad SPI
JTAG
GPIO
ADC/DAC
EFUSE
CAN
BPF*
LPO
(NINA-W106)
PCB trace antenna
(NINA-W101
)
Flash (16/32 Mbit)
Quad SPI