SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R26 Design-in
Page 132 of 217
Guidelines for dual SIM card / chip connection
Two SIM card / chip can be connected to the modules’ SIM interface as illustrated in the circuit of Figure 65.
SARA-G3 and SARA-U2 modules do not support the usage of two SIM at the same time, but two SIM can be
populated on the application board providing a proper switch to connect only the first SIM or only the second
SIM per time to the SIM interface of the SARA-G3 and SARA-U2 modules as described in Figure 65.
SARA-G3 modules do not support SIM hot insertion / removal: the module is able to properly use a SIM only if
the SIM / module physical connection is provided before the module boot and then held for normal operation.
Switching from one SIM to another one can only be properly done within one of these two time periods:
after module switch-off by the AT+CPWROFF and before module switch-on by PWR_ON
after network deregistration by AT+COPS=2 and before module reset by AT+CFUN=16 or RESET_N
SARA-U2 modules support SIM hot insertion / removal on the SIM_DET pin: if the feature is enabled using the
specific AT commands (refer to sections 1.8.2 and 1.11, and to the u-blox AT Commands Manual [3], +UGPIOC,
+UDCONF commands), the switch from first SIM to the second SIM can be properly done when a Low logic level
is present on the SIM_DET pin (‘SIM not inserted’ = SIM interface not enabled), without the necessity of a
module re-boot, so that the SIM interface will be re-enabled by the module to use the second SIM when a High
logic level will be re-applied on the SIM_DET pin.
In the application circuit example represented in Figure 65, the application processor will drive the SIM switch
using its own GPIO to properly select the SIM that is used by the module. Another GPIO may be used to handle
the SIM hot insertion / removal function of SARA-U2 modules, which can also be handled by other external
circuits or by the cellular module GPIO according to the application requirements.
The dual SIM connection circuit described in Figure 65 can be implemented for SIM chips as well, providing
proper connection between SIM switch and SIM chip as described in Figure 63.
If it is required to switch between more than two SIMs, a circuit similar to the one described in Figure 65 can be
implemented: for example, in the event of four SIM circuit, using a proper 4-pole 4-throw switch (or,
alternatively, four 1-pole 4-throw switches) instead of the suggested 4-pole 2-throw switch.
Follow these guidelines connecting the module to two SIM connectors:
Use a proper low on resistance (i.e. few ohms) and low on capacitance (i.e. few pF) 2-throw analog switch
(e.g. Fairchild FSA2567) as SIM switch to ensure high-speed data transfer according to SIM requirements.
Connect the contacts C1 (VCC) of the two UICC / SIM to the VSIM pin of the module by means of a proper
2-throw analog switch (e.g. Fairchild FSA2567).
Connect the contact C7 (I/O) of the two UICC / SIM to the SIM_IO pin of the module by means of a proper
2-throw analog switch (e.g. Fairchild FSA2567).
Connect the contact C3 (CLK) of the two UICC / SIM to the SIM_CLK pin of the module by means of a
proper 2-throw analog switch (e.g. Fairchild FSA2567).
Connect the contact C2 (RST) of the two UICC / SIM to the SIM_RST pin of the module by means of a
proper 2-throw analog switch (e.g. Fairchild FSA2567).
Connect the contact C5 (GND) of the two UICC / SIM to ground.
Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close to
the related pad of the two SIM connectors, to prevent digital noise.
Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line
(VSIM, SIM_CLK, SIM_IO, SIM_RST), very close to each related pad of the two SIM connectors, to prevent
RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holders.
Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on
each externally accessible SIM line, close to each related pad of the two SIM connectors, according to the
EMC/ESD requirements of the custom application.
Limit capacitance and series resistance on each SIM signal (SIM_CLK, SIM_IO, SIM_RST) to match the
requirements for the SIM interface (27.7 ns is the maximum allowed rise time on the SIM_CLK line, 1.0 µs is
the maximum allowed rise time on the SIM_IO and SIM_RST lines).
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