ViewSonic VG181 - Page 22

Service Manual ViewSonic
VG181 July 2000 - Version 1.0
THEORY OF CIRCUIT OPERATION
The DS90C383 transmitter converts 28 bits of COMS/TTL data into four LVDS
(Low Voltage Differential Signaling) data streams. A phase-locked signal is
transmitied in parallel with the data streams over a fifth LVDS link for every cycle
of the transmit clock. 28 bits of input data are sampled and transmitted. The
DS90CF384 receiver converts the LVDS data streams back into 28 bits of
CMOS/TTL. data. At a transmit clock frequency of 65MHz, 24 bits of RGB data and
4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CONTROL) are
transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65MHz clock,
the data throughput is 227 Megabytes per second. The Transmitter is offered with
programmable edge data strobes for convenient interface with a variety of graphics
controllers. The Transmitter can be programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin.
This chipset is an ideal means to solve EMI and cable size problems associated
with wide, high speed TTL interfaces.
Features
m Programmable Transmitter(DS90C383) strobe select (Rising or Falling edge
strobe)
Single +3.3V supply
Low power CMOS design (<250Mw TYP total)
Power-down mode (<0.5mW total)
Single pixel per clock XGA(1024x768) ready
Supports VGA, SVGA, XGA and higher addressability
Up to 227 Megabytes/sec bandwidth
Narrow bus reduces cable size
345mV swing LVDS devices for low EMI
PLL requires no external components
Low profile 56-lead TSSOP package
Failing edge data strobe Receiver(DS90CF384)
Compatible with TIA/EIA-644 LVDS standard and the VESA FPDI-2(draft)
standard
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Confidential - Do Not Copy