ViewSonic VG181 - Page 23

ViewSonic . Service Manual
July 2000 - Version 1.0 VG181
THEORY OF CIRCUIT OPERATION
DS90C383 Block Diagrams
DS90C383
CMOS/TTL
INPUTS
DATA
(LVDS)
RED
GRN
(140 to 455 Mbit/s -
On Each LVDS -
Channel)
BLU
FPLINE (HSYNC)
FPFRAME
(VSYNC)
DRDY (Data Enable)
CNTL
FPSHIFT IN
(TRANSMIT CLOCK IN) gc tri 0
(20 to 65MHz)
POWER DOWN
DS90C383 Pin Description - FPD Link Transmitter
| PinName | vo | No. Description
TxIN 28 | TTL level input. This includes: 8 Red, 8 Green, 8 Blue and 4
control lines - FPLINE, FPFRAME, DRAY AND CNTL {also
referred to as HSYNC, VSYNC, Data Enable, CNTL).
TxOUT+ Ean Positive LVDS differential data output.
TxOUT- Ox ode 4 Negative LVDS differential data output.
FPSHIFT IN a fa | TTL level clock input. The falling edge acts as data strobe.
[ReBUT lt | a | Programmable strobe select.
TxCLK OUT+ | O | 1 | Positive LVDS differential clock output.
TxCLK OUT- pot 1 Negative LVDS differential clock output.
/PWR DOWN TTL level input Assertion (low input) tri-states the output,
‘ensuring low current at power down.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Page 21
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