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Watlow 988 series - Page 74

Watlow 988 series
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A.4
Data Communications with the Watlow Series 988 Family Appendix
DLE 1.6-1.7
download sequence
981-984 5.1
986-989 6.6
996-999 7.1
E
EIA-485 1.3, 2.1, A.1
EIA-485 wiring 2.3
Elapsed Jump Count [EJC]
981-984 5.5
End of Text <ETX> 1.6-1.7, 4.2
End of Transmission <EOT> 1.6-1.7
End Set Point [ENSP]
981-984 5.5
ENQ 1.6-1.7
enquiry <ENQ> 1.7
EOT 1.6-1.7
ER2 A.1
Error
Analog Input [ER]
981-984 5.5
986-989 6.10
996-999 7.4
Codes A.1
Communications [ER2]
981-984 5.6
986-989 6.10
996-999 7.5
Latching Enable [ERR]
981-984 5.6
986-989 6.10
996-999 7.5
establish communications 4.5
ETX 1.6-1.7, 4.2
even parity 1.5
Event 3 Output State [ENT3]
981-984 5.5
Event 4 Output State [ENT4]
981-984 5.5
Event Input 1
Function [EI1]
981-984 5.5
986-989 6.10
996-999 7.4
Status [EI1S]
981-984 5.5
986-989 6.10
996-999 7.4
Event Input 2
Function [EI2]
981-984 5.5
986-989 6.10
Status [EI2S]
981-984 5.5
986-989 6.10
example format 4.2
F
Factory Test Date [DATE]
981-984 5.4
986-989 6.9
996-999 7.3
Filter Time Constant
981-984 [FTR1] 5.6
986-989 [FTR1], [FTR2] 6.11
996-999 [FTR1], [FTR2] 7.5
flow control 4.2
front panel, controller 3.2
G
Global Menu Lockout [GLBL]
986-989 6.11
996-999 7.5
Guaranteed Soak Deviation [GSD]
981-984 5.6
H
Hardware Type
Input 1 [ITY1]
981-984 5.7
986-989 6.12
996-999 7.7
Input 2 [ITY2]
981-984 5.7
986-989 6.13
996-999 7.7
Output 1 [OTY1]
981-984 5.9
986-989 6.14
996-999 7.8
Output 2 [OTY2]
981-984 5.9
986-989 6.14
996-999 7.8
Output 3 [OTY3]
981-984 5.9
986-989 6.14
996-999 7.8
Output 4 [OTY4]
981-984 5.9
986-989 6.14
996-999 7.8
hex string 4.2
hexadecimal [hex] 1.4
High Power Limit [HIP]
981-984 5.6
986-989 6.11
Hysteresis
Output 1
981-984 [HYS1] 5.6
986-989 [HYS1] 6.11
996-999 [HY1A], [HY1B] 7.5
Output 2
981-984 [HYS2] 5.6
986-989 [HYS2] 6.11
996-999 [HY2A], [HY2B] 7.5
Output 3 [HYS3]
981-984 5.6
986-989 6.11
996-999 7.5
I
Idle Set Point [IDSP]
981-984 5.7
986-989 6.11
increment key 2.1
Input 1
Calibration Offset [CAL1]
981-984 5.4
986-989 6.8
996-999 7.3
Decimal Point [DEC1]
981-984 5.5
986-989 6.9
996-999 7.4
Event Function [EI1]
981-984 5.5
986-989 6.10
996-999 7.4
Event Status [EI1S]
981-984 5.5
986-989 6.10
996-999 7.4
Hardware Type [ITY1]
981-984 5.7
986-989 6.12
996-999 7.7
Range High [RH1]
981-984 5.10
986-989 6.15
996-999 7.9
Range Low [RL1]
981-984 5.10
986-989 6.16
996-999 7.9
RTD Calibration [RTD1]
981-984 5.10
986-989 6.16
996-999 7.10
Type [IN1]
981-984 5.7
986-989 6.11
996-999 7.6
Value [C1]
981-984 5.4
986-989 6.8
996-999 7.3
Input 2
Calibration Offset [CAL2]
981-984 5.4
986-989 6.8
996-999 7.3
Decimal Point [DEC2]
986-989 6.9
996-999 7.4
Event Function [EI2]
981-984 5.5
986-989 6.10
Event Status [EI2S]
981-984 5.5
986-989 6.12
Hardware Type [ITY2]
981-984 5.7
986-989 6.13
996-999 7.7
Range High [RH2]
981-984 5.10
986-989 6.15
996-999 7.9
Range Low [RL2]
981-984 5.10
986-989 6.16
996-999 7.9
RTD Calibration [RTD2]
986-989 6.16
996-999 7.10
Type [IN2]
981-984 5.7
986-989 6.12
996-999 7.6
Value [C2]
981-984 5.4
986-989 6.8
996-999 7.3
Index

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