4.2inch e-Paper Module User Manual
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⚫ DC is data/command control pin, when DC = 0, write command, when DC = 1,
write data.
⚫ SCLK is the SPI communication clock.
⚫ SDIN is the data line from the master to the slave in SPI communication.
SPI communication has data transfer timing, which is combined by CPHA and CPOL.
1. CPOL determines the level of the serial synchronous clock at idle state. When
CPOL = 0, the level is Low. However, CPOL has little effect to the transmission.
2. CPHA determines whether data is collected at the first clock edge or at the second
clock edge of serial synchronous clock; when CPHL = 0, data is collected at the
first clock edge.
⚫ There are 4 SPI communication modes. SPI0 is commonly used, in which CPHL =
0, CPOL = 0.
As you can see from the figure above, data transmission starts at the first falling edge
of SCLK, and 8 bits of data are transferred in one clock cycle. In here, SPI0 is in used,
and data is transferred by bits, MSB.
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