XFX GeForce 9300 Motherboard
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charge before DRAM refresh, refresh may be incomplete
and DRAM may fail to retain data. This item applies only
when synchronous DRAM is installed in the system.
tRAS
When the Memory Timings sets to [Manual], this field is
adjustable. This setting determines the time RAS takes to
read from and write to memory cell.
tRRD
When the Memory Timings sets to [Manual], the field is
adjustable. Specifies the active-to-active delay of different
banks. Time interval between a read and a precharge
command.
tRC
When the Memory Timings sets to [Manual], the field is
adjustable. The row cycle time determines the minimum
number of clock cycles a memory row takes to complete a
full cycle, from row activation up to the precharging of
the active row.
tWR
When the Memory Timings sets to [Manual], the field is
adjustable. Minimum time interval between end of write
data burst and the start of a precharge command. Allows
sense amplifiers to restore data to cells.
tWTR
When the Memory Timings sets to [Manual], the field is
adjustable. Minimum time interval between the end of
write data burst and the start of a column-read command.
It allows I/O gating to overdrive sense amplifiers before
read command starts.
tREF
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