Xilinx SmartLynq Plus User Manual

Table 10: Signal Descriptions (cont'd)
Pin Name Direction Description
23 TRACEDATA15 Input Trace data 15
24 TRACEDATA3 Input Trace data 3
25 TRACEDATA14 Input Trace data 14
26 TRACEDATA2 Input Trace data 2
27 TRACEDATA13 Input Trace data 13
28 TRACEDATA1 Input Trace data1
29 TRACEDATA12 Input Trace data12
30 LOGIC0 Output Logic bit 0. Pulled to GND through 4.7 KΩ resistor
31 TRACEDATA11 Input Trace data 11
32 LOGIC1 Output Logic bit 1 Pulled to GND through 4.7 KΩ resistor
33 TRACEDATA10 Input Trace data 10
34 LOGIC2 Output Logic bit 2. Pulled up to VTREF through 4.7 KΩ resistor
35 TRACEDATA9 Input Trace data 9
36 TRACECTL Input Trace control
37 TRACEDATA8 Input Trace data 8
38 TRACEDATA0 Input Trace data 0
Chapter 10: Parallel Debug Interface
UG1514 (v1.0) March 8, 2021 www.xilinx.com
SmartLynq Module+ 37
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Xilinx SmartLynq Plus Specifications

General

Brand	Xilinx
Model	SmartLynq Plus
Category	Network Hardware
Language	English