Xilinx SmartLynq Plus User Manual

Chapter 9
HSDP Target Interface
HSDP support can be added to a board by adding a USB-C connector and connecng up the high
speed lines to Versal ACAP dedicated HSDP GT ports, as shown in the following gure. By
making use of the custom protocol support allowed by the USB-C/USB 3.0 specicaon, a board
can readily have basic HSDP support with just the addion of the HSDP connector. However,
because it is necessary to rst inialize a Versal ACAP with an inial image, a target must have
the JTAG interface connected to the SmartLynq+ Module. When performing the inial bring up
of a Versal ACAP it is also helpful to make use of a UART to gain further observability of the
system. For this reason it is very useful to integrate all these debug capabilies through a single
connector. As a result the HSDP debug connector has a superset opon that fully enables you to
gain essenal observability with a minimum connector footprint with an added benet of
scalable debug support.
Chapter 9: HSDP Target Interface
UG1514 (v1.0) March 8, 2021 www.xilinx.com
SmartLynq Module+ 28
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Xilinx SmartLynq Plus Specifications

General

Brand	Xilinx
Model	SmartLynq Plus
Category	Network Hardware
Language	English