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Xilinx Spartan-6 LX9 User Manual

Xilinx Spartan-6 LX9
28 pages
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Copyright © 2015 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are property of their respective owners.
Avnet Electronics Marketing 10 of 28 Rev D 24 Apr 2015
Bank0
44 IOs
(3.3V)
Bank2
44 IOs
(3.3V)
VCCINT
and
Ground
Bank1
56 IOs
(3.3V)
Bank3
56 IOs
(1.8V)
SPI Flash
(6 I/Os)
LPDDR MCB
(41 I/Os)
User DIP (4 I/Os)
RZQ (1 I/O)
Ethernet (18 I/Os)
Config (4 I/Os)
Clk (1 I/O)
User LEDs
(4 I/Os)
User PBs
(1 I/O)
UART (2-4 I/Os)
2x6 PMODx2
( 16 I/Os)
Figure 4 – XC6SLX9 CSG324 I/O Allocation

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Xilinx Spartan-6 LX9 Specifications

General IconGeneral
Logic Cells9152
Registers11440
Slices1430
Block RAM (Kb)576
DSP48A1 Slices16
Number of I/O Banks4
Input Delay BlocksYes
Output Delay BlocksYes
Maximum Single-Ended Output Current (mA)24
I/O Standards SupportedLVTTL, LVCMOS, PCI, SSTL, HSTL
Maximum Differential Output Current (mA)12