Yamaha 01x - Page 135

HGFEDCBA
1
2
3
4
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O1X
5
■ BLOCK DIAGRAM 003
28CA1-8825603-003 1
mLAN-NC1
[MIDI Packet]
Xtal
20MHz
mLAN-PH2
YTS440B-F
[AUDIO Packet]
PHY
MD8408B
1
2
ACTIVE
EEPROM
16K
DRIVER
DRIVER
Exp. I/O port
REGULATOR
PLL
TLC2932
LPF
MIDI (UART)
I/F
mLAN2 I/F
16bit
CPU bus
I/F
Digital
Audio
I/F
IC8 (256P)
X1
48
110, 111
76
Xtal
24.576MHz
X2
CN2
CN3
42–45
29, 30
38–41
IC10 (64P)
ACTV
LD4
IC9 (8P)
ICLK <24.576MHz>
232
89
14, 15
5, 6
33 3
6
90
29
33
32
35
31
21
36
40
88
93
90
106
101
57
58
69
3
5
6
1
4
56
3.072MHz, 48kHz for MIDI Packet
GUID/Module Name/Config.
SCLK <49.512MHZ>
Up to 40MHz by Internal PLL
Up to 393.216MHz by Internal PLL
PHY – LINK I/F
IC2
IC14A (100P)
*(CPLD)-#1
*(CPLD)-#1
*(CPLD)-#1
IC7 (208P)
PLL-Response
PLL-Response
Low Jitter/Vari Pttch Following
IC14B (100P)
IC14C (100P)
CN6 (100P)
PLL-Lock
PLL-Lock
512fs
IC2 (14P)
+5V
+3.3V
TR1
CV
IC4
1
3
VCO
PHASE
COMPARATOR
PCB (Divider Out)
PCA (SYT-Match)
Async (Hold)
ACTV
ROOT
Async (Hold)
ACTV
ROOT
Packet-Master/Slave
Packet-Master/Slave
Packet-Master/Slave
mLAN-Word Clock Direction
CPU Bus @mLAN-NC1’s CPU core
Isochrous Bus
MIDI IN/OUT (5 port)
mLAN-Word Clock Slected
/RESET
Tx Digital Audio (24ch) (max)
Rx Digital Audio (16ch)
WCK (Fs)
WCK (Fs)
+5V
+3.3V
MCK (256Fs) BCK (64Fs)
MCK (256Fs @Fs = 44.1 – 48kHz, 128Fs @ Fs = 2 – 96kHz))
*Digital Audio Format : 24bit/MSB-First/Left Justfied/2ch@line
IEE1394 (S400)
MLN2