Yamaha DSP-AX1600 - Page 63

RX-V1600/DSP-AX1600
63
RX-V1600/
DSP-AX1600
IC301: M30845FJGP (FUNCTION P.C.B)
16-bit Microprocessor
PowerOn Standby MCUSleep [OFF]
No. Port Name
Terminal Name I/O
Function
(P.C.B.)
SO
SO
DA
DA
TMR
I
TMR
O
TMR
O
O
O
O
O
MCU
MCU
O
O
MCU
MCU
MCU
MCU
MCU
IRQ
IRQ
IRQ
IRQ
TMR
O
I
I / I
TMR
O
TMR
I / I
SI
SO
SO / SO
MCU
SI / SI
MCU
SO / SO
I / O
SO
SI
SO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
MCU
MCU
O
O
MCU
MCU
MCU
MCU
MCU
I
IRQ
IRQ
IRQ
O
O
O
O / O
O
O
O
I / I
O
O
SO / SO
MCU
SI / SI
MCU
SO / SO
I / O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
MCU
MCU
O
O
MCU
MCU
MCU
MCU
MCU
I
IRQ
IRQ
IRQ
O
O
O
O / O
O
O
O
O / O
O
O
O / SO
MCU
SI [O] / SI
MCU
O / SO
I [O] / O
O
O
O
Data transmits to VIDEO_CPU
Clock transmits to VIDEO_CPU
Limiter control output
Temperature control FAN control output
HDMI MUTE input
VIDEO_CPU 232C communication line enable control
VIDEO_CPU response return input
VIDEO_CPU reset
VIDEO_CPUI transmission demand input
Digital FULL MUTE (HI=MUTE)
* Chip enable for S, C, SW2chDAC (Reserve)
2shDAC (PCM1791A) * Chip enable for 6
* Chip enable for YSS930 (#0 / #1 Common)
External data bus width change: 16 bit
Processor mode selection: Single chip mode/Hi: To boot mode
with a built-in flash/At the time of hard reset: It is to boot mode at
P50=H, P55=L, and CNVss=H
DIR initial clear
TI initial clear
Remote control pulse input 1
Remote control pulse input 2/Remote control pulse input for zone
remote control
RS232C/YDC reception detection
Vertical sync pulse INT
Chip enable for TI decoder DSP DA601
TI BUSY detection/CDDA write-in DATA input
DA601 GP0(0): TI DA601 Serial Ready / DRI WCK output: DIR
WCK input (WCK input for CDDA writing)
TI (DA601) interruption
Chip enable for DIR
DIR interruption
RS232C flash write-in mode detection / MULTI CH INPUT key
detection
DABIC IC RxD (XM data reception) / 1.5k pull up to +5SPC
DABIC IC TxD / 1.5k pull up to +5SPC
RS232C: Usual RS-232C asynchronous communication data
output / YDC: Transmitting terminal for AF220
Usual RS-232C asynchronous communication data input / At the
time of 232C driver OFF, since driver output is set to HiZ, it is
LowFix processing / Transmitting terminal for AF220
Usual RS-232C asynchronous communication RTS output /
Clock input for AF220
Usual RS-232C asynchronous communication CTS input / At the
time of 232C driver OFF, since driver output is set to HiZ, it is
LowFix processing / BUSY output for AF220
Serial data output to DIR, TI (DA601), YSS930, and DAC / DIR/
YSS: 4M, LSBF/TI: 1M, MSBF
Serial data reception to DIR, TI (DA601), YSS930, and DAC /
DIR/YSS: 4M, LSBF/TI: 1M, MSBF
Serial Clock output to DIR, TI (DA601), YSS930, and DAC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
TXDH (MtoV)
CLKH
LIMIT
FAN
HDIMT
/EN232C
HRES
/ICH
HREQ
DMT
/CSDAC3
/CSDAC2
/CSDAC1
/CSY
BYTE
CNVss
/ICD
/ICTI
RESET
Xout
Vss
Xin
Vcc
NMI
REM1
REM2
RXDR
/VSYNC
/CSTI
TIBUSY
SPIRDY
/INTTI
/CSDIR
/INTDIR
BT232C
DRXM
DTXM
TXDR
Vcc
RXDR
Vss
RTS / CLKF
CTS / YDCBUSY
TXDD
RXDD
CLKD
TXD4
CLK4
DA1
DA0
SDA3/TXD3/TB2in
SCL3/RXD3/TB1in
TB0in
P146
P145
P144
P143
P142
P141
P140
BYTE
CNVss
P87
P86
RESET
Xout
Vss
Xin
Vcc
NMI
INT2
INT1
INT0
TA4in
P80
TA3in/P77
P76
TA2in
P74
TA1in
P72/CLK2/TA1out
P71/RxD2/SCO2
P70/TXD2/SDA2
P67/TxD1
Vcc
P66/RxD1
Vss
P65/CLK1
P64/CTS1/RTS1/
P63/TxD0
P62/RxD0
P61/CLK0