4.3 CPU Unit Specifications
Performance Specifications
4-7
Ladder Pro-
grams
Number of Startup Draw-
ings (DWG.A)
64
Number of steps per drawing: 4,000
Number of Interrupt Draw-
ings (DWG.I)
64
Number of High-speed
Scan Drawings (DWG.H)
1000
Number of Low-speed
Scan Drawings (DWG.L)
2000
Number of User Function
Drawings
2000
Motion Pro-
grams
Number of Programs 512
Total of all programs listed below:
• Motion main programs
• Motion subprograms
• Sequence main programs
• Sequence subprograms
Number of Groups 16 −
Number of Tasks 32 −
Number of Nesting Levels
for IF Instructions
8 −
Number of Nesting Levels
for MSEE Instructions
8 −
Number of Parallel Forks
Per Task
8
Select from the following four options:
• Main: 4 forks, Sub: 2 forks
• Main: 8 forks
• Main: 2 forks, Sub: 4 forks
• Sub: 8 forks
Number of Simultaneously
Controlled Axes Per Task
32 axes −
Registers
S Registers 64 Kwords −
M Registers 1 Mword Battery backup
G Registers 2 Mwords No battery backup
I/O Registers 64 Kwords −
Motion Registers 32 Kwords −
C Registers 16 Kwords −
# Registers 16 Kwords −
D Registers 16 Kwords −
Data Types
Bit (B) Supported. 0, 1
Integer (W) Supported. -32,768 to 32,767
Double-length Integer (L) Supported. -2,147,483,648 to 2,147,483,647
Quadruple-length Integer
(Q)
Supported.
-9,223,372,036,854,775,808 to
9,223,372,036,854,775,807
Single-precision Real
Number (F)
Supported. ± (1.175E-38 to 3.402E+38), 0
Double-precision Real
Number (D)
Supported. ± (2.225E-308 to 1.798E+308), 0
Addresses (A) Supported. 0 to 16,777,214
Index Registers
Subscript i Supported.
Special registers for offsetting addresses.
Subscripts i and j function identically.
Subscript j Supported.
Array Registers Supported. Used to handle registers as arrays
Continued on next page.
Continued from previous page.
Item
Specification
Remarks
CPU-201 CPU-202
To Next Page