ABB rec670 - Page 11

Scheme communication logic for residual overcurrent
protection ECPSCH ...............................................................59
Local acceleration logic ZCLCPLAL.......................................59
Secondary system supervision....................................................59
Overview................................................................................59
Current circuit supervision CCSRDIF ....................................60
Fuse failure supervision SDDRFUF.......................................60
Control.........................................................................................60
Overview................................................................................60
Autorecloser SMBRREC .......................................................60
Synchrocheck and energizing check SESRSYN ...................60
Tap changer control and supervision, 6 binary inputs
TCMYLTC..............................................................................60
Tap changer control and supervision, 32 binary inputs
TCLYLTC ..............................................................................61
Automatic voltage control for tapchanger, single control
TR1ATCC ..............................................................................61
Automatic voltage control for tapchanger, parallel
control TR8ATCC ..................................................................61
Monitoring....................................................................................61
Overview................................................................................61
Event counter CNTGGIO.......................................................61
Fault locator LMBRFLO..........................................................61
Logic............................................................................................62
Overview................................................................................62
Tripping logic SMPPTRC ......................................................62
Trip matrix logic TMAGGIO....................................................62
LogicGate...............................................................................62
LogicRSMemory_qt................................................................62
LogicSRMemory.....................................................................62
LogicSRMemory_qt................................................................62
LogicTimerSet........................................................................63
LogicTimerSet_qt...................................................................63
Activate setting group.......................................................................63
Language..........................................................................................63
Section 10
Diagnose IED status.......................................................65
Read internal events.........................................................................65
Find available functions....................................................................65
Section 11 Test the IED...................................................................67
Overview...........................................................................................67
IED test mode...................................................................................68
View binary input values...................................................................68
Overview......................................................................................68
Table of contents
5
Operator's manual