TPU2000/2000R Modbus/Modbus Plus/ Modbus TCP/IP Automation Guide
282
4.6 Transmit Programmable Output AND/OR Select ( 3 4 6 )
Bit = 0, Selected inputs are ORed together.
Bit = 1, Selected inputs are ANDed together.
Index byte is the offset into the TPU's logical output structure.
Bit
Logical Output
0 not used, reserved for fixed DIFF TRIP
1 Contact OUT5
2 Contact OUT7
3 Contact OUT4
4 Contact OUT6
5 Contact OUT3
6 Contact OUT2
7 Contact OUT1
8 spare
9 spare
10 spare
11 spare
12 spare
13 spare
14 spare
15 spare
Index
Output Definition
00 DIFF Fixed Diff Trip, 87T or 87H
01 ALARM Fixed Self Check Alarm
02 87T Percentage Differential Trip
03 87H High Set Inst Diff Trip
04 2HROA 2nd Harm Restraint Output Alarm
05 5HROA 5th Harm Restraint Alarm
06 AHROA All Harm Restraint Alarm
07 TCFA Trip Circuit Failure Alarm
08 TFA Trip Failure Alarm
09 51P-1 Wdg 1 Phase Time OC Trip
10 51P-2 Wdg 2 Phase Time OC Trip
11 50P-1 1st Wdg 1 Phase Inst OC Trip
12 150P-1 2nd Wdg 1 Phase Inst OC Trip
13 50P-2 1st Wdg 2 Phase Inst OC Trip
14 150P-2 2nd Wdg 2 Phase Inst OC Trip
15 51N-1 Wdg 1 Neutral Time OC Trip
16 51G-2 Wdg 2 Ground Time OC Trip
17 50N-1 1st Wdg 1 Neutral Inst OC Trip
18 150N-1 2nd Wdg 1 Neutral Inst OC Trip
19 50G-2 1st Wdg 2 Ground Inst OC Trip
20 150G-2 2nd Wdg 2 Ground Inst OC Trip
21 46-1 Wdg 1 Neg Sequence Time OC Trip
22 46-2 Wdg 2 Neg Sequence Time OC Trip
23 87T-D Percentage Differential Disabled Alarm
24 87H-D High Set Inst Diff Disabled Alarm
25 51P-1D Wdg 1 Phase Time OC Disabled Alarm
26 51P-2D Wdg 2 Phase Time OC Disabled Alarm
27 51N-1D Wdg 1 Neutral Time OC Disabled Alarm
28 51G-2D Wdg 2 Ground Time OC Disabled Alarm
29 50P-1D 1st Wdg 1 Phase Inst OC Disabled Alarm
30 50P-2D 1st Wdg 2 Phase Inst OC Disabled Alarm
31 50N-1D 1st Wdg 1 Neutral Inst OC Disabled Alarm
32 50G-2D 1st Wdg 2 Ground Inst OC Disabled Alarm
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