AIC Auriga - Page 37

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Chapter 4. BIOS Conguration SettingsAuriga User Manual
DDR4 Common
Options
DRAM Timing
Conguration
I Accept
ProcODT Processor ODT
Tcwl
Minimum CAS
Write Latency
Range
Trtp
Read to Precharge
Delay
Trdwr tWRTTO time.
Twrrd
Read delay
when accessing
different DIMMs.
TwrwrSc
TwrwrSd
TwrwrDd
TrdrdSc
TrdrdSd
TrdrdDd
Write to iwrite
timing same
DIMM same chip
select.
Tcke
CKE minimum
high and low
pulse width in
memory clock
cycles.
DDR4 Common
Options
Common Ras ECC Conguration
DRAM ECC
Symbol Size
x4
x8
Auto
DRAM ECC Enable
Auto
Enable
Disable
Security
TSME
Auto
Enable
Disable
Data Scramble
Auto
Enable
Disable
DRAM Memory
Mapping
Chip select
Interleaving
Auto
Disable
Bank Group
Swap
Auto
Enable
Disable
NVDIMM Read only.