so critical throughout this circuit that parts that are even slightly out of spec will cause failures. This is
due to the fact that propagation delay times are not only significant, but inherently part of the design.
If the logic seems a bit confusing at first, it helps to remember that many of the target signals are
active low.
The M3 also utilizes a double buffering system to ensure smooth operation. (i.e. the ASIC
reads it's instructions from bank A while the 8031 writes to bank B. At the end of the of the current
sample period, the banks are switched.).The "FLIP" bit is used to keep track of this. Once the 8031
has finished writing a control program into the SRAM, it toggles the FLIP SeND (U21 pin 12) line. It
can then poll FLIP ReCieVe (U20 pin 9) to determine when the flip actually takes place (the end of
the current sample, when ASIC A7 goes from high to low, strobing the positive edge triggered clock
of U21B {pin 11} via U18 {pins 1, 2, and 3 wired as Inverter}). All leftover SRAM space is used for
the 8031 to store variables for it's own use.
There are three states of operation.
$ ASIC Reads from memory
$ 8031 Reads from memory
$ 8031 Writes to memory
In all of these operations the DeLaYeD 6MHz clock determines which device will be
controlling the SRAM. Any time that DLYD 6MHZ is low, the ASIC has control. When asic clock is
high, the 8031 is allowed to access the SRAM. DLYD 6MHZ is derived from the 6MHz clock via U16
1A & 1B. In this configuration, the only difference between the 6MHz clock and DLYD 6MHZ is the
propagation delay of U16. This is done to ensure that
data and address lines have had time to settle before the
SRAM is accessed. U13-U14 are used to multiplex
between the ASIC and 8031 address busses and are
switched directly by DLYD 6MHZ. Note that all access to
the SRAM from the 8031 is memory mapped (see
section 4.3 for a description of the process).
4.4.1 ASIC Reads From Memory
Since the ASIC only needs to read memory, the
logic is very simple. Anytime that DLYD 6MHZ is low, the
SRAM's output enable (OE pin 20) is guaranteed to be
low (when pin 5 of U18 goes low, it's output will go high,
and U18 {pins 8,9, and 10} invert it to a low). At the same
time The SRAM's Write Enable line (pin 21) is
guaranteed to be high (U16 is always in the "A" position,
and input 2A (pin 5) is tied high. A0-A7 are pr
esented to
the
SRAM directly from the ASIC. At this point the U15
A/B select line (pin 1) is guaranteed to be high (via U16 4A) so that A9-A10 are guaranteed to be low
(via U15 3B and 4B). A8 depends on the state of the FLIP bit arriving from U20 (pin 9) via U16
switch 3 (pins 9, 10, and 11), and determines which "bank" the ASIC is currently reading from. The
SRAM data buss can now be read by the ASIC normally.
Diagram 4
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