M0–M1 Files and G Files B–3
Publication
17476.6 - July 1996
Monitoring Bit Addresses
For SLC 5/02 processors, the M0/M1 Monitoring option is always
disabled. (This processor does not allow you to monitor the actual
state of each addressed M0/M1 address.) For SLC 5/03 and SLC
5/04 processors, you can choose to disable or enable the monitoring
option by selecting
[F6], System Config, from the APS main menu.
M0/M1 Monitoring Option Disabled
When you monitor a ladder program in the Run or Test mode with
the M0/M1 Monitoring option disabled, the following bit
instructions, addressed to an M0 or M1 file, are indicated as false
regardless of their actual true/false logical state.
When you are monitoring the ladder program in the Run or Test mode, the
APS or HHT display does not show these instructions as being true when the
processor evaluates them as true.
] [
Mf:e.s
b
]/[
Mf:e.s
b
( )
Mf:e.s
b
(L)
Mf:e.s
b
(U)
Mf:e.s
b
f
= file (0 or 1)
If you need to show the state of the M0 or M1 addressed bit, you can
transfer the state to an internal processor bit. This is illustrated
below, where an internal processor bit is used to indicate the
true/false state of a rung.
This rung will not show its true rung state because the EQU instruction is always shown
as true and the M0 instruction is always shown as false.
OTE instruction B3/2 has been added to the rung. This instruction shows the true or
false state of the rung.
EQU
EQUAL
Source A N7:12
Source B N7:3
] [
B3
0
] [
B3
1
( )
M0:3.0
1
( )
M0:3.0
1
] [
B3
0
] [
B3
1
EQU
EQUAL
Source A N7:12
Source B N7:3
( )
B3
2
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