Preface
MicroLogix 1000 Programmable Controllers User Manual
8–6
32-Bit Addition and Subtraction
You have the option of performing 16-bit or 32-bit signed integer addition and
subtraction. This is facilitated by status file bit S:2/14 (math overflow selection bit).
Math Overflow Selection Bit S:2/14
Set this bit when you intend to use 32-bit addition and subtraction. When S:2/14 is
set, and the result of an ADD, SUB, MUL, DIV, or NEG instruction cannot be
represented in the destination address (due to math underflow or overflow):
• The overflow bit S:0/1 is set.
• The overflow trap bit S:5/0 is set.
•
The destination address contains the unsigned truncated least significant 16 bits
of the result.
When S:2/14 is reset (default condition), and the result of an ADD, SUB, MUL,
DIV, or NEG instruction cannot be represented in the destination address (due to
math underflow or overflow):
• The overflow bit S:0/1 is set.
• The overflow trap bit S:5/0 is set.
• The destination address contains 32767 if the result is positive or –32768 if the
result is negative.
Note that the status of bit S:2/14 has no effect on the DDV instruction. Also, it has
no effect on the math register content when using MUL and DIV instructions.
Example of 32-bit Addition
The following example shows how a 16-bit signed integer is added to a 32-bit
signed integer. Remember that S:2/14 must be set for 32-bit addition.
Note that the value of the most significant 16 bits (B3:3) of the 32-bit number is
increased by 1 if the carry bit S:0/0 is set and it is decreased by 1 if the number
being added (B3:1) is negative.
To avoid a major error from occurring at the end of the scan, you must unlatch
overflow trap bit S:5/0 as shown.
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