Using High-Speed Counter Instructions
12–23
High-Speed Counter Interrupt Enable (HSE)
and Disable (HSD)
These instructions enable or disable a high-speed counter interrupt when a high
preset, low preset, overflow, or underflow is reached. Use the HSD and HSE in
pairs to provide accurate execution for your application.
The Counter referenced by these instructions have the same address as the HSC
instruction counter and is fixed at C5:0.
Using HSE
Operation
When the high-speed counter interrupt is enabled, user subroutine (program file 4)
is executed when:
• A high or low preset is reached.
• An overflow or underflow occurs.
When in Test Single Scan mode and in an idle condition, the high-speed counter
interrupt is held off until the next scan trigger is received from the programming
device. The high-speed counter accumulator counts while idle.
If the HSE is subsequently executed after the pending bit is set, the interrupt is
executed immediately.
The default state of the high-speed counter interrupt is enabled (the IE bit is set
to 1).
Programming
Execution Times
(µsec) when:
True False
10.00 7.00
8.00 7.00
HSE
HSD
HSE
HSC INTERRUPT ENABLE
COUNTER C5:0
HSD
HSC INTERRUPT DISABLE
COUNTER C5:0
efesotomasyon.com - Allen Bradley,Rockwell,plc,servo,drive
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