Preface
MicroLogix 1000 Programmable Controllers User Manual
12–4
• Counter Up Enable Bit CU (bit 15) is used with all of the high-speed counter
types. If the HSC instruction is true, the CU bit is set to one. If the HSC
instruction is false, the CU bit is set to zero. Do not write to this bit.
• Counter Down Enable Bit CD (bit 14) is used with the Bidirectional
Counters (modes 3–8). If the HSC instruction is true, the CD bit is set to one.
If the HSC instruction is false, the CD bit is set to zero. Do not write to this bit.
• High Pr
eset Reached Bit DN
(bit 13) For the Up Counters (modes 1 and 2),
this bit is an edge triggered latch bit. This bit is set when the high preset is
reached. You can reset this bit with an OTU instruction or by executing an
RAC or RES instruction.
The DN bit is a reserved bit for all other Counter options (modes 3–8).
• Overflow Occurred Bit OV (bit 12) For the Up Counters (modes 1 and 2),
this bit is set by the controller when the high preset is reached if the DN bit is
set.
For the Bidirectional Counters (modes 3–8), the OV bit is set by the controller
after the hardware accumulator transitions from 32,767 to –32,768. Y
ou can
reset this bit with an OTU instruction or by executing an RAC or RES
instruction for both the up and bidirectional counters.
• Underflow Occurred Bit UN (bit 11) is a reserved bit for the Up Counters
(modes 1 and 2). Do not write to this bit.
For the Bidirectional Counters (modes 3–8), the UN bit is set by the controller
when the hardware accumulator transitions from –32,768 to +32,767. Y
ou can
reset this bit with an OTU instruction or by executing an RAC or RES
instruction.
• Update High-Speed Counter Accumulator Bit UA (bit 10) is used with an
OTE instruction to update the instruction image accumulator value with the
hardware accumulator value. (The HSC instruction also performs this operation
each time the rung with the HSC instruction is evaluated as true.)
• Accumulator ≥ High Preset Bit HP (bit 9) is a reserved bit for all Up
Counters(modes 1 and 2).
For the Bidirectional Counters (modes 3–8), if the hardware accumulator
becomes greater than or equal to the high preset, the HP bit is set. If the
hardware accumulator becomes less than the high preset, the HP bit is reset by
the controller. Do not write to this bit. (Exception – you can set or reset this bit
during the initial configuration of the HSC instruction. See page 12–6 for
more information.)
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