Altera Cyclone V - Using the EPCQ Flash Memory

2–14 Chapter 2: Board Components
FPGA Configuration
Cyclone V GT FPGA Development Board August 2017 Altera Corporation
Reference Manual
Figure 2–4 shows the PFL configuration.
f For more information on the following topics, refer to the respective documents:
■ Board Update Portal, PFL design, and flash memory map storage, refer to the
Cyclone V GT FPGA Development Kit User Guide.
■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.
Using the EPCQ Flash Memory
To enable FPGA configuration using the EPCQ device, you must reconfigure the MAX
V device with a specific hardware design, which you can download.
For further information, refer to “Configuring the MAX V Device to Program EPCQ”
on page 2–11.
Figure 2–4. PFL Configuration
MAX V CPLD
5M2210 System Controller
Cyclone V FPGA
FPGA_DATA [15:0]
FPGA_DCLK
FLASH_A [26:1]
FLASH_D [15:0]
DATA [15:0]
DCLK
nSTATUS
nCONFIG
CONF_DONE
MSEL1
MSEL2
MSEL4
MSEL0
MSEL3
MSEL[4:0] also
connects to the
MAX V CPLD
2.5 V
1 kΩ
1 kΩ
nCE
CFI Flash
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_A [26:1]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_WPn
FLASH_ADVn
FPGA_nCONFIG
FPGA_CONF_DONE
FLASH_RYBSYn
FLASH_RYBSYn
FPGA_nSTATUS
1.8 V
10 kΩ
FLASH_ADVn
FLASH_CLK
FLASH_CLK
FLASH_RSTn
FLASH_RESETn
PS Port
Flash Interface
100 Ω56.2 Ω
56.2 Ω
50 MHz
100 MHz
2.5 V
2.5 V
2.5 V
MAX_ERROR
MAX_LOAD
MAX_CONF_DONE
ASSP_MODE
FACTORY_USER
CLK_ENABLE
CLK_SEL
MAX_RESETn
CPU_RESETn
PGM_CONFIG
PGM_SEL
PGM_LED0
PGM_LED1
PGM_LED2
DIP Switch
DIP Switch
10 kΩDNI
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