Altera Cyclone V User Manual

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User Guide
Cyclone V Hard IP for PCI Express
Document last updated for Altera Complete Design Suite version:
Document publication date:
11.1
November 2011
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UG-01110-1.0
Cyclone V Hard IP for PCI Express User Guide

Altera Cyclone V Specifications

General

Family	Cyclone V
Manufacturer	Intel (formerly Altera)
Process Technology	28 nm
Logic Elements	25K to 301K
Transceivers	Up to 12
Transceiver Speed	Up to 5 Gbps
HPS Clock Speed	Up to 925 MHz
Ethernet MAC	1 or 2
USB OTG	1
CAN	2
Package Options	FBGA, UBGA
Operating Temperature	-40°C to 100°C (Industrial)
Core Voltage	1.1V
HPS	Dual-core ARM Cortex-A9 MPCore

Summary

Datasheet

Features

Details the key features of the Cyclone V Hard IP for PCI Express IP core.

IP Core Verification

Getting Started

MegaWizard Plug-In Manager Design Flow

Guides through customizing the IP core using the MegaWizard Plug-In Manager.

Qsys Design Flow

Guides through customizing the IP core and testbench using the Qsys system integration tool.

Parameter Settings

System Settings

Defines the overall system parameters for the PCI Express IP core.

Port Functions

IP Core Architecture

Key Interfaces

Introduces the functionality of the interfaces shown in the block diagram.

Protocol Layers

Describes the Transaction Layer, Data Link Layer, and Physical Layer in detail.

IP Core Interfaces

Avalon-ST RX Interface

Describes the signals that comprise the Avalon-ST RX Datapath.

Avalon-ST TX Interface

Describes the signals that comprise the Avalon-ST TX Datapath.

Register Descriptions

Configuration Space Register Content

Shows the common Configuration Space header and provides detailed tables for registers.

Correspondence between Configuration Space Registers and PCIe Spec 2.1

Provides a comprehensive correspondence between registers and PCIe Base Specification descriptions.

Reset and Clocks

Reset

Covers the functional aspects of the reset circuitry for the Cyclone V Hard IP for PCI Express.

Clocks

Describes the clock domains and requirements for the Cyclone V Hard IP for PCI Express.

Transaction Layer Protocol (TLP) Details

Supported Message Types

Describes the message types supported by the Hard IP, including INTX and Power Management.

Transaction Layer Routing Rules

Error Handling

Physical Layer Errors

Data Link Layer Errors

Transaction Layer Errors