Altera Cyclone V - Avalon-ST TX Interface

5–8 Chapter 5: IP Core Interfaces
Avalon-ST TX Interface
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
Figure 5–8 illustrates back-to-back transmission on the 64-bit Avalon-ST RX interface
with no idle cycles between the assertion of
rx_st_eop and rx_st_sop .
f For a complete description of the TLP packet header formats, refer to Appendix A,
Transaction Layer Packet (TLP) Header Formats.
Avalon-ST TX Interface
Table 5–4 describes the signals that comprise the Avalon-ST TX Datapath. The TX data
signal can be 64 or 128 bits.
Figure 5–8. 64-Bit Avalon-ST Interface Back-to-Back Transmission
coreclkout
rx_st_data[63:0]
rx_st_sop
rx_st_eop
rx_st_empty
rx_st_ready
rx_st_valid
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Table 5–4. 64- or 128-Bit Avalon-ST TX Datapath (Part 1 of 3)
Signal Width Dir
Avalon-ST
Type
Description
tx_st_data 64 I data
Data for transmission. Transmit data bus. Refer to
Figure 5–9 through Figure 5–13 for the mapping of TLP
packets to
tx_st_data and examples of the timing of the
64-bit interface.
The Application Layer must provide a properly formatted
TLP on the TX interface. The mapping of message TLPs is
the same as the mapping of Transaction Layer TLPs with 4
dword headers. The number of data cycles must be correct
for the length and address fields in the header. Issuing a
packet with an incorrect number of data cycles results in
the TX interface hanging and unable to accept further
requests.
tx_st_sop 1I
start of
packet
Indicates first cycle of a TLP when asserted in the same
cycle with
tx_st_valid .
tx_st_eop 1I
end of
packet
Indicates last cycle of a TLP when asserted in the same
cycle with
tx_st_valid .