5–36 Chapter 5: IP Core Interfaces
Test Signals
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
Test Signals
The
test_in
bus provides run-time control and monitoring of the internal state of the
Cyclone V Hard IP for PCI Express. Table 5–23 describes the test signals.
c Altera recommends that you use the
test_in
signals for debug or non-critical status
monitoring purposes such as LED displays of PCIe link status. They should not be
used for design function purposes. Use of these signals will make it more difficult to
close timing on the design. The test signals have not been rigorously verified and will
not function as documented in some corner cases.
The debug signals provided on
test_out
are not available in the current release.
Table 5–23 describes the
test_in
bus signals. In Qsys these signals have the prefix,
hip_ctrl_.
Table 5–23. Test Interface Signals
(1)
,
(2)
Signal I/O Description
test_in[31:1]
I
[0]–Simulation mode. This signal can be set to 1 to accelerate
initialization by reducing the value of many initialization counters.
[4:1] Reserved.
These signals are not supported in the current release. You must
drive them to all 0’s.
[6:5] Compliance test mode. Disable/force compliance mode:
■ bit 0–When set, prevents the LTSSM from entering compliance
mode. Toggling this bit controls the entry and exit from the
compliance state, enabling the transmission of Gen1 and Gen2
compliance patterns.
■ bit 1–Forces compliance mode. Forces entry to compliance mode
when timeout is reached in polling.active state (and not all lanes
have detected their exit condition).
■ [31:7] Reserved.
O When set to 1, the PIPE interface is in simulation mode.
I
Compliance mode test switch. When set to 1, the IP core is in
compliance mode which is used for Compliance Base Board testing
(CBB) testing. When set to 0, the IP core is in operates normally.
Connect this signal to a switch to turn on and off compliance mode.
Refer to the PCI Express High Performance Reference Design for an
actual coding example to specify CBB tests.
lane_act[3:0]
Lane Active Mode: This signal indicates the number of lanes that
configured during link training. The following encodings are defined:
■ 4’b0001: 1 lane
■ 4’b0010: 2 lanes
■ 4’b0100: 4 lanes
Notes to Table 5–23:
(1) All signals are per lane.
(2) Refer to “PIPE Interface Signals” on page 5–33 for definitions of the PIPE interface signals.
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